# US 2014/0153319 A1 · Semiconductor memory device

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- Number: US 2014/0153319 A1
- Document ID: US20140153319A1
- Status: Published application
- Kind: A1
- Application number: 14/171,812
- Filed: 2014-02-04
- Published: 2014-06-05
- Earliest claimed: 2010-10-29
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Toshihiko Saito
- Web page: https://patentgrep.com/patent/US20140153319A1

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/565: {using capacitive charge storage elements}
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/33: {the capacitor extending under the transistor}
- H10D 1/714: {having horizontal extensions}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 84/813: {Combinations of field-effect devices and capacitor only}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes a bit line; two or more word lines; and a memory cell including two or more sub memory cells that each include a transistor and a capacitor. One of a source and a drain of the transistor is connected to the bit line, the other of the source and the drain of the transistor is connected to the capacitor, a gate of the transistor is connected to one of the word lines, and each of the sub memory cells has a different capacitance of the capacitor.

## Claims

### Claim 1

A semiconductor memory device comprising:
a bit line;
a plurality of word lines; and
a memory cell comprising a plurality of sub memory cells, the sub memory cells each comprising a transistor and a capacitor,
wherein one of a source and a drain of the transistor is electrically connected to the bit line,
wherein the other of the source and the drain of the transistor is electrically connected to the capacitor,
wherein a gate of the transistor is electrically connected to one of the plurality of word lines, and
wherein capacitances of the capacitors in the plurality of sub memory cells are different from each other.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1,
wherein a capacitance of a capacitor in a sub memory cell in the n-th row of the plurality of sub memory cells is 2n-1 times as large as a capacitance of a capacitor having a smallest capacitance of the capacitors,
wherein n is a natural number.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein an active layer of the transistor comprises an oxide semiconductor.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the plurality of sub memory cells are provided to overlap with each other.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein the memory cell is overlapped with another memory cell having a function similar to that of the memory cell.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein a capacitance of a capacitor having a smallest capacitance of the capacitors is more than or equal to 0.1 fF and less than or equal to 1 fF.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, wherein each of the plurality of sub memory cells comprises a DRAM.

### Claim 8

A semiconductor memory device comprising:
a bit line;
a plurality of word lines;
a memory cell comprising a plurality of sub memory cells, the sub memory cells each comprising a transistor and a capacitor; and
an amplifier,
wherein one of a source and a drain of the transistor in each of the plurality of sub memory cells is electrically connected to a first terminal of the amplifier,
wherein the other of the source and the drain of the transistor is electrically connected to the capacitor,
wherein a gate of the transistor is electrically connected to one of the plurality of word lines, and
wherein capacitances of the capacitors in the plurality of sub memory cells are different from each other.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8,
wherein a capacitance of a capacitor in a sub memory cell in the n-th row of the plurality of sub memory cells is 2n 1 times as large as a capacitance of a capacitor having a smallest capacitance of the capacitors,
wherein n is a natural number.

### Claim 10 (depends on 8)

The semiconductor memory device according to claim 8, wherein an active layer of the transistor comprises an oxide semiconductor.

### Claim 11 (depends on 8)

The semiconductor memory device according to claim 8, wherein the plurality of sub memory cells are provided to overlap with each other.

### Claim 12 (depends on 8)

The semiconductor memory device according to claim 8, wherein the memory cell is overlapped with another memory cell having a function similar to that of the memory cell.

### Claim 13 (depends on 8)

The semiconductor memory device according to claim 8, wherein a capacitance of a capacitor having a smallest capacitance of the capacitors is more than or equal to 0.1 fF and less than or equal to 1 fF.

### Claim 14 (depends on 8)

The semiconductor memory device according to claim 8, wherein each of the plurality of sub memory cells comprises a DRAM.