# US 2014/0153315 A1 · Semiconductor memory apparatus, refresh method and system

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- Number: US 2014/0153315 A1
- Document ID: US20140153315A1
- Status: Published application
- Kind: A1
- Application number: 14/095,269
- Filed: 2013-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Research & Business Foundation Sungkyunkwan University
- Applicants: Research & Business Foundation Sungkyunkwan University
- Inventors: Keewon KWON; Jongmin BAEK; Dongjin SEO
- Web page: https://patentgrep.com/patent/US20140153315A1

## CPC

- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 29/50008: {of impedance}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse}
- G11C 2029/0409: {Online test}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Disclosed are a semiconductor memory apparatus, and refresh method and system. The semiconductor memory apparatus includes: a memory cell array including a plurality of resistive memory cells; and a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells. Therefore, the refresh of the resistive memory is efficiently performed, and as a result, performance deterioration may be minimized, and a lifespan of the device may be extended.

## Claims

### Claim 1

A semiconductor memory apparatus, comprising:
a memory cell array including a plurality of resistive memory cells; and
a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells.

### Claim 2 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
the control block controls a first refresh mode and a second refresh mode to be performed by classifying a first and a second level by comparing a bit value of the digital code value with a reference value and grouping the plurality of memory cells.

### Claim 3 (depends on 2)

The semiconductor memory apparatus of claim 2, wherein:
the control block classifies a memory cell among the plurality of memory cells, in which a degree in which a resistance state deviates from a target value is smaller than a predetermined threshold value, into a first level by comparing the bit value of the digital code value with the reference value, and
classifies a memory cell among the plurality of memory cells, in which a degree in which a resistance state deviates from a target value is larger than a predetermined threshold value, into a second level by comparing the bit value of the digital code value with the reference value.

### Claim 4 (depends on 2)

The semiconductor memory apparatus of claim 2, wherein:
the first refresh mode associated with the resistive memory cell of the first level is a mode in which a hidden refresh is performed with respect to each resistive memory cell in an idle state, and
the second refresh mode associated with the resistive memory cell of the second level is a mode in which the refresh is compulsively performed with respect to the entire memory while blocking a system access.

### Claim 5 (depends on 2)

The semiconductor memory apparatus of claim 2, wherein:
when the control block performs an incremental step pulse programming (ISPP) mode during the refresh process,
the control block controls the resistive memory cell of the first level to perform the ISPP mode while sequentially increasing a voltage magnitude or a voltage applying time based on a predetermined initial voltage magnitude or initial voltage applying time, and
controls the resistive memory cell of the second level to perform the ISPP mode while applying the initial voltage magnitude or the initial voltage applying time which is larger or longer than the resistive memory cell of the first level.

### Claim 6 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
the control block controls the refresh operation to be performed with respect to all the plurality of resistive memory cells based on a power-up operation or a periodically monitoring operation, or the refresh operation to be performed for each corresponding cell by monitoring resistance states of the plurality of resistive memory cells every read operation.

### Claim 7 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
the control block controls at least one of an applying voltage magnitude and a voltage applying time for the plurality of resistive memory cells to be variable during the refresh operation with respect to the plurality of resistive memory cells based on the digital code value.

### Claim 8 (depends on 1)

The semiconductor memory apparatus of claim 1, further comprising:
an analog to digital converter (ADC) configured to generate the digital code value.

### Claim 9 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
the control block classifies one state value (including SET (1) or RESET (0)) of the plurality of resistive memory cells into at least two levels based on the digital code value, and allocates refresh schedules of the plurality of resistive memory cells to be different from each other.

### Claim 10 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
a built-in-self-test (BIST) for monitoring the plurality of resistive memory cells is used.

### Claim 11 (depends on 1)

The semiconductor memory apparatus of claim 1, wherein:
when the plurality of memory cells connected to one word line simultaneously performs the write operation by sharing one power line, the control block controls magnitudes of the initial voltages applied through the bit lines to vary according to the digital code value while the initial applying voltages through the word lines are the same as each other during the refresh operation with respect to the plurality of memory cells connected to one word line.

### Claim 12

A refresh method of a semiconductor memory apparatus, comprising:
generating a digital code value reflecting resistance states of a plurality of resistive memory cells; and
controlling at least one of a mode and a schedule of a refresh operation to be variable with respect to the plurality of resistive memory cells based on the generated digital code value.

### Claim 13 (depends on 12)

The refresh method of a semiconductor memory apparatus of claim 12, wherein:
the controlling includes controlling a first refresh mode and a second refresh mode to be performed by classifying a first and a second level by comparing a bit value of the digital code value with a reference value and grouping the plurality of memory cells.

### Claim 14 (depends on 13)

The refresh method of a semiconductor memory apparatus of claim 13, wherein:
the controlling includes classifying a memory cell among the plurality of memory cells, in which a degree in which a resistance state deviates from a target value is smaller than a predetermined threshold value, into a first level by comparing the bit value of the digital code value with the reference value, and
classifying a memory cell among the plurality of memory cells, in which a degree in which a resistance state deviates from a target value is larger than a predetermined threshold value, into a second level by comparing the bit value of the digital code value with the reference value.

### Claim 15 (depends on 13)

The refresh method of a semiconductor memory apparatus of claim 13, wherein:
the first refresh mode associated with the resistive memory cell of the first level is a mode in which a hidden refresh is performed with respect to each resistive memory cell in an idle state, and
the second refresh mode associated with the resistive memory cell of the second level is a mode in which the refresh is compulsively performed with respect to the entire memory while blocking a system access.

### Claim 16 (depends on 13)

The refresh method of a semiconductor memory apparatus of claim 13, wherein:
the controlling includes when performing an incremental step pulse programming (ISPP) mode during the refresh process,
controlling the resistive memory cell of the first level to perform the ISPP mode while sequentially increasing a voltage magnitude or a voltage applying time based on a predetermined initial voltage magnitude or initial voltage applying time, and
controlling the resistive memory cell of the second level to perform the ISPP mode while applying the initial voltage magnitude or the initial voltage applying time which is larger or longer than the resistive memory cell of the first level.

### Claim 17 (depends on 12)

The refresh method of a semiconductor memory apparatus of claim 12, wherein:
a built-in-self-test (GIST) for monitoring the plurality of resistive memory cells is used.

### Claim 18 (depends on 12)

The refresh method of a semiconductor memory apparatus of claim 12, wherein:
the controlling includes when the plurality of memory cells connected to one word line simultaneously performs the write operation by sharing one power line,
controlling magnitudes of the initial voltages applied through the bit lines to be variable according to the digital code value while the initial applying voltages through the word lines are the same as each other in the ISPP mode with respect to the plurality of memory cells.

### Claim 19

A semiconductor memory system, comprising:
a semiconductor memory apparatus; and
a processor for controlling a write operation and a verify read operation of the semiconductor memory apparatus,
wherein the semiconductor memory apparatus includes
a memory cell array including a plurality of resistive memory cells; and
a control block configured to control at least one of a mode and a schedule of a refresh operation for the plurality of memory cells to be variable based on digital code values reflecting resistance states of the plurality of resistive memory cells.

### Claim 20 (depends on 19)

The semiconductor memory system of claim 19, wherein:
the control block controls a first refresh mode and a second refresh mode to be performed by classifying a first and a second level by comparing a bit value of the digital code value with a reference value and grouping the plurality of memory cells.