# US 2014/0153314 A1 · System and a method for designing a hybrid memory cellwith memristor and complementary metal-oxide semiconductor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153314 A1 - Document ID: US20140153314A1 - Status: Published application - Kind: A1 - Application number: 13/691,830 - Filed: 2012-12-02 - Published: 2014-06-05 - Earliest claimed: 2012-12-02 - Assignees: Khalifa University of Science, Technology & Research (KUSTAR) - Inventors: Shehadah Mohammad Baker; Dirar Al-Homouz - Web page: https://patentgrep.com/patent/US20140153314A1 ## CPC - G11C 13/004: {Reading or sensing circuits or methods} - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The embodiments herein relates to a hybrid non-volatile memory cell system and architecture for designing integrated circuits. The system comprises CMOS access transistor connected to a memristor which stores a data based on a resistance. The system has a word line for accessing the hybrid memory and two bit lines carrying data of mutually opposite values for transferring a data from the memory. The two terminals of the transistor are connected respectively to a first terminal of the memristor and to a first bit line. The gate terminals of the transistors are coupled together to form a word line. The access transistors control the two bit lines during a read and write operation. A control logic performs a read and write operation with the hybrid memory cells. The memory architecture prevents a power leakage during data storage and controls a drift in a state during a read process. ## Claims ### Claim 1 A hybrid non-volatile memory cell system and a hybrid memory array architecture for designing an integrated circuit (IC), the system comprising: a set of at-least one or more transistors, wherein the set of at-least one or more transistors are Complementary Metal Oxide Semiconductor (CMOS); a memristor for storing a data based on a resistance value; a word line for accessing the hybrid non-volatile memory system; and a set of at-least two bit lines for transferring a data from a hybrid non-volatile memory system; wherein the memristor is connected to the at-least one or more transistors, and wherein a gate terminals of the at-least one or more transistors are coupled together. ### Claim 2 (depends on 1) The system according to claim 1, wherein the set of two bit line (terminal) are a first bit line and a second bit line, wherein a data carried in the first bit line and a data carried in the second bit line are separated by memristor wherein the data get written to or read from using said set of two bit line. ### Claim 3 (depends on 1) The system according to claim 1, wherein the set of at-least one or more transistors are access transistors, wherein the access transistors control the set of two bit lines during a read and write operation, wherein the read operation retrieves a data from the hybrid non-volatile memory cell, and wherein the write operation provides a data to the hybrid non-volatile memory cell for storing. ### Claim 4 (depends on 1) The system according to claim 1, wherein the hybrid non-volatile memory cell comprises at-least one transistor and at-least one memristor, wherein a first terminal of the transistor is connected to a first terminal of the memristor and a second terminal of the transistor is connected to a first bit line, and wherein a gate terminal of the transistor is used as a word line, wherein the word line provides an access to the hybrid non-volatile memory system, and wherein a second terminal of the memristor is used as a second bit line. ### Claim 5 (depends on 1) The system according to claim 1, wherein the hybrid non-volatile memory cell comprises a first transistor, a second transistor and at-least one memristor, wherein the memristor is connected between the first transistor and the second transistor, wherein a first terminal of the first transistor is connected to a first bit line, and wherein a second terminal of the second transistor is connected to a second bit line, and wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled, wherein the coupled gate terminals are used as a word line, wherein the word line provides an access to the hybrid non-volatile memory cell. ### Claim 6 (depends on 1) The system according to claim 1, wherein a data stored in the hybrid non-volatile memory cell is a logic one (1), and wherein a data stored in the hybrid non-volatile memory cell is a logic zero (0). ### Claim 7 (depends on 1) The system according to claim 1, wherein a plurality of hybrid non-volatile memory cells are designed to provide a hybrid memory architecture, wherein the hybrid memory architecture prevents a leakage of a power during a data storage, and wherein the hybrid memory array architecture controls a drifting of a read state during a read access. ### Claim 8 A control logic and a control logic circuit system for controlling an access to a hybrid memory cell, comprising: a read logic for reading a data from a hybrid non-volatile memory cell, wherein the read logic is designed to satisfy stability requirement; a write logic, wherein the write logic prevents a write operation of a data when the write data is same as a data stored in the hybrid non-volatile memory cell, wherein the control logic performs a read operation and a write operation with one or more hybrid memory cells; ### Claim 9 (depends on 8) The system according to claim 8, wherein the control logic is based on Complementary Metal Oxide Semiconductor (CMOS) logic, wherein the control logic controls all peripheral circuits to the hybrid memory array architecture, and wherein the control logic isolates the hybrid memory array architecture from external circuits. ### Claim 10 (depends on 8) The system according to claim 8, wherein the control logic uses the read and write logic to minimize instability of a data stored in the hybrid non-volatile memory cells, and wherein a direction of read current is selected to reflect an impact on a state drift. ### Claim 11 A method of designing an efficient hybrid non-volatile memory cell and a hybrid memory array architecture, the method comprises: connecting a one or more transistors to a memristor, wherein the memristor is a memory element; providing a word line, wherein the word line is a gate terminal of the one or more transistors; providing a set of two bit lines, wherein a value of a data carried in the set of two bit lines are mutually opposite to each other; creating a control logic circuit, wherein the control logic controls an operation related with an accessing of the hybrid non-volatile memory cells; connecting a pluralities of hybrid non-volatile memory cells and forming a hybrid memory array architecture; and accessing the hybrid memory array architecture for a read and write operation. ### Claim 12 (depends on 11) The method according to claim 11, wherein the hybrid non-volatile memory cell comprises at-least one transistor and at-least one memristor, wherein a first terminal of the transistor is connected to a first terminal of the memristor and a second terminal of the transistor is connected to a first bit line, and wherein a gate terminal of the transistor is used as a word line, wherein the word line provides an access to the hybrid non-volatile memory system, and wherein a second terminal of the memristor used as a second bit line. ### Claim 13 (depends on 11) The method according to claim 11, wherein the hybrid non-volatile memory cell comprises a first transistor, a second transistor and at-least one memristor, wherein the memristor is connected between the first transistor and the second transistor, wherein a first terminal of the first transistor is connected to a first bit line, and wherein a second terminal of the second transistor is connected to a second bit line, and wherein a gate terminals of the first transistor and a gate terminal of the second transistor are coupled, wherein the coupled gate terminals are used as a word line, wherein the word line provides an access to the hybrid non-volatile memory cell. ### Claim 14 (depends on 11) The method according to claim 11, wherein the control logic performs a read operation and a write operation with the hybrid non-volatile memory cells in the hybrid memory array architecture. ### Claim 15 (depends on 11) The method according to claim 11, wherein the control logic minimizes a state drift during a read operation from the hybrid non-volatile memory cell, wherein the state drift is minimized by reading the data with a decaying voltage, wherein a direction of read is from OFF state to ON state. ### Claim 16 (depends on 11) The method according to claim 11, wherein the control logic uses a single ended scheme for a reading operation, wherein the single ended scheme senses and develops a small difference with respect to a reference voltage to recognize a stored data in the hybrid non-volatile memory cell. ### Claim 17 (depends on 11) The method according to claim 11, wherein a write operation to the hybrid memory array architecture is executed by turning ON a hybrid memory cell upon selecting a respective word line, and wherein a current is passed depending on the data to be stored in the hybrid non-volatile memory cell, and wherein a direction of current determines a memristor resistance and in turn the value stored in the hybrid non-volatile memory cell. ### Claim 18 (depends on 11) The method according to claim 11, wherein a read operation from the hybrid memory architecture is executed by setting the word line of a preferred hybrid non-volatile memory cell to logic one (1), wherein a second bit line is pre-charged to logic one (1) and a first bit line is driven to logic zero (0), and wherein the second bit line is discharged through the memristor, wherein the data is read by comparing a voltage at the second bit line to a similar circuit with known value of memristor using a sense amplifier.