# US 2014/0153313 A1 · System and Methods Using a Multiplexed Reference for Sense Amplifiers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153313 A1 - Document ID: US20140153313A1 - Status: Published application - Kind: A1 - Application number: 13/689,869 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Intel Deutschland GmbH; Infineon Technologies AG - Inventors: El Mehdi Boujamaa; Cyrille Dray - Web page: https://patentgrep.com/patent/US20140153313A1 ## CPC - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 11/1673: {Reading or sensing circuits or methods} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence) - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase. ## Claims ### Claim 1 A sense amplifier system comprising: a switch component coupled to a first path, a second path; a memory cell; a first reference cell; and a second reference cell; and wherein a switch component is configured to switch connections between the first and second reference cells, the memory cell and the first path and the second path according to a sampling phase and an amplification phase. ### Claim 2 (depends on 1) The system of claim 1, wherein the switch component is configured to connect the second path to the memory cell during the sampling phase. ### Claim 3 (depends on 2) The system of claim 2, wherein the switch component is configured to connect the second path to the second reference cell during the amplification phase. ### Claim 4 (depends on 2) The system of claim 2, wherein the switch component is a multiplexor. ### Claim 5 (depends on 1) The system of claim 1, wherein the first path is a sense path and the second path is a reference path. ### Claim 6 (depends on 1) The system of claim 1, wherein the first path is a reference path and the second path is a sense path. ### Claim 7 (depends on 1) The system of claim 1, wherein the first path and the second path include a cascode component. ### Claim 8 (depends on 7) The system of claim 7, further comprising bias capacitors coupled to the cascode component, wherein the bias capacitors are configured to set gate voltages of cascode transistors of the cascode component. ### Claim 9 (depends on 1) The system of claim 1, wherein the first path includes an offset capacitor configured to sense an offset during the sampling phase. ### Claim 10 (depends on 1) The system of claim 1, further comprising a common mode feedback structure coupled to the first path and the second path, the common mode feedback structure configured to provide a common mode feedback mode of operation. ### Claim 11 (depends on 10) The system of claim 10, further comprising a latch structure coupled to the common mode feedback structure, the first path, and the second path, the latch structure configured to provide a latch mode of operation. ### Claim 12 (depends on 1) The system of claim 1, wherein the first reference cell is a high resistivity reference cell. ### Claim 13 (depends on 1) The system of claim 1, wherein the first reference cell is a low resistivity reference cell and the second reference cell is a high resistivity reference cell, wherein the first reference cell is configured to enable a low resistivity reference current and the second reference cell is configured to enable a high resistivity reference current. ### Claim 14 (depends on 1) The system of claim 1, wherein the first transistor path includes a first differential output node and the second transistor path includes a second differential output node, wherein the first and second differential output nodes provide an output voltage during the amplification phase representative of a logical content of the memory cell. ### Claim 15 A sense amplifier system comprising: a sense path including a first transistor coupled to a first data transistor; a reference path including a second transistor coupled to a second data transistor; and a switch component coupled to the sense path and the reference path, the switch component configured to connect a memory cell to the reference path during a first phase and to connect the memory cell to the sense path during a second phase. ### Claim 16 (depends on 15) The system of claim 15, wherein the first phase is a sampling phase. ### Claim 17 (depends on 15) The system of claim 15, wherein the sense path is configured to have a first reference current and the reference path is configured to have a data current during the first phase. ### Claim 18 (depends on 17) The system of claim 17, wherein the sense path is configured to have the data current and the reference path is configured to have a second reference current during the second phase, wherein the second reference current is varied from the first reference current. ### Claim 19 (depends on 18) The system of claim 18, wherein the first reference current is a high resistivity reference current and the second reference current is a low resistivity reference current. ### Claim 20 A method of operating a sense amplifier, the method comprising: generating a first reference current; generating a second reference current; generating a data current; and generating an output voltage according to the data current, the first reference current, and the second reference current. ### Claim 21 (depends on 20) The method of claim 20, further comprising providing a memory cell, wherein the memory cell is utilized to generate the data current and the output voltage represents a content of the memory cell. ### Claim 22 (depends on 20) The method of claim 20, wherein generating the first reference circuit comprises using a low resistivity reference cell. ### Claim 23 (depends on 20) The method of claim 20, wherein generating the first reference current comprises connecting a sense path to the first reference cell. ### Claim 24 (depends on 22) The method of claim 22, wherein generating the second reference current comprises connecting a reference path to the second reference cell.