# US 2014/0153307 A1 · Driver device for power factor correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153307 A1 - Document ID: US20140153307A1 - Status: Published application - Kind: A1 - Application number: 14/095,664 - Filed: 2013-12-03 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Samsung Electro-Mechanics Co., Ltd. - Applicants: Samsung Electro-Mechanics Co., Ltd. - Inventors: In Wha JEONG; Chang Jae HEO; Bum Seok SUH; Jae Hyun LIM - Web page: https://patentgrep.com/patent/US20140153307A1 ## CPC - H02M 1/0085: {Partially controlled bridges} - H02M 1/4225: {using a non-isolated boost converter} - H02M 7/217: using semiconductor devices only - H02M 3/158: including plural semiconductor devices as final control devices for a single load - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract There is provided a driver device for a power factor correction circuit including first and second main switches that are switched on and off with a phase difference therebetween, and first and second auxiliary switches that provide conduction paths of surplus voltage in the first and second main switches before the first and second main switches are switched on, the driver device including: an input unit receiving a plurality of input signals; and an output unit outputting a first control signal for the first main switch, a second control signal for the second main switch, a third control signal for the first auxiliary switch, and a fourth control signal for the second auxiliary switch based on a plurality of input signals. ## Claims ### Claim 1 A driver device for a power factor correction circuit including first and second main switches that are switched on and off with a phase difference therebetween, and first and second auxiliary switches that provide conduction paths of surplus voltage in the first and second main switches before the first and second main switches are switched on, the driver device comprising: an input unit receiving a plurality of input signals; and an output unit outputting a first control signal for the first main switch, a second control signal for the second main switch, a third control signal for the first auxiliary switch, and a fourth control signal for the second auxiliary switch based on a plurality of input signals. ### Claim 2 (depends on 1) The driver device of claim 1, wherein the input unit receives first and second input signals. ### Claim 3 (depends on 2) The driver device of claim 2, wherein one of the first and second input signals is a pulse width modulation (PWM) signal, and the remaining signal is a high signal. ### Claim 4 (depends on 3) The driver device of claim 3, further comprising a PWM selecting unit selectively passing a PWM signal based on the first and second input signals, the PWM signal being a first internal signal. ### Claim 5 (depends on 4) The driver device of claim 4, further comprising a pulse generating unit outputting a second internal signal having a phase delayed with regard to a phase of the first internal signal and a third internal signal having a delayed phase and a reduced pulse width with regard to the first internal signal based on the first internal signals. ### Claim 6 (depends on 5) The driver device of claim 5, wherein the phase of the second internal signal is delayed with regard to that of the third internal signal. ### Claim 7 (depends on 5) The driver device of claim 5, further comprising: a checking unit outputting a fourth internal signal including input signal information based on the first and second input signals. ### Claim 8 (depends on 7) The driver device of claim 7, wherein the checking unit outputs a high signal in the case that the first input signal is a PWM signal, and outputs a low signal in the case that the second input signal is a PWM signal. ### Claim 9 (depends on 7) The driver device of claim 7, further comprising a main signal generating unit outputting first and second control signals based on the second and fourth internal signals. ### Claim 10 (depends on 9) The driver device of claim 9, wherein the main signal generating unit, in the case that the fourth internal signal is a high signal, outputs the second internal signal as the first control signal and the high signal as the second control signal. ### Claim 11 (depends on 9) The driver device of claim 9, wherein the main signal generating unit, in the case that the fourth internal signal is a low signal, outputs a high signal as the first control signal and the second internal signal as the second control signal. ### Claim 12 (depends on 9) The driver device of claim 9, further comprising an auxiliary signal generating unit outputting third and fourth control signals based on the third and fourth internal signals. ### Claim 13 (depends on 12) The driver device of claim 12, wherein the auxiliary signal generating unit, in the case that the fourth internal signal is a high signal, outputs the third internal signal as the third control signal and a low signal as the fourth control signal. ### Claim 14 (depends on 12) The driver device of claim 12, wherein the auxiliary signal generating unit, in the case that the fourth internal signal is a low signal, outputs the low signal as the third control signal and the third internal signal as the fourth control signal. ### Claim 15 A driver device for a power factor correction circuit, comprising: a PWM selecting unit selecting one of a plurality of input signals to output a first internal signal; a pulse generating unit outputting a second internal signal having a phase delayed with regard to a phase of the first internal signal and a third internal signal having a delayed phase and a reduced pulse width with regard to the first internal signal based on the first internal signal output from the PWM selecting unit; a checking unit outputting a fourth internal signal including information on input signals based on the plurality of input signals; a main signal generating unit outputting a first control signal for a first main switch and a second control signal for a second main switch based on the second and fourth internal signals; and an auxiliary signal generating unit outputting a third control signal for a first auxiliary switch and a fourth control signal for a second auxiliary switch based on the third and fourth internal signals. ### Claim 16 (depends on 15) The driver device of claim 15, wherein the plurality of input signals includes first and second input signals, wherein one of the first and second input signals is a pulse width modulation (PWM) signal, and the remaining signal is a high signal. ### Claim 17 (depends on 15) The driver device of claim 15, wherein the first internal signal is a PWM signal. ### Claim 18 (depends on 15) The driver device of claim 15, wherein a phase of the second internal signal is delayed with regard to that of the third internal signal. ### Claim 19 (depends on 16) The driver device of claim 16, wherein the checking unit outputs a high signal in the case that the first input signal is a PWM signal, and outputs a low signal in the case that the second input signal is a PWM signal. ### Claim 20 (depends on 15) The driver device of claim 15, wherein the main signal generating unit, in the case that the fourth internal signal is a high signal, outputs the second internal signal as the first control signal and the high signal as the second control signal. ### Claim 21 (depends on 15) The driver device of claim 15, wherein the main signal generating unit, in the case that the fourth internal signal is a low signal, outputs a high signal as the first control signal and the second internal signal as the second control signal. ### Claim 22 (depends on 15) The driver device of claim 15, wherein the auxiliary signal generating unit, in the case that the fourth internal signal is a high signal, outputs the third internal signal as the third control signal and a low signal as the fourth control signal. ### Claim 23 (depends on 15) The driver device of claim 15, wherein the auxiliary signal generating unit, in the case that the fourth internal signal is a low signal, outputs the low signal as the third control signal and the third internal signal as the fourth control signal.