# US 2014/0153210 A1 · Advanced device assembly structures and methods

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- Number: US 2014/0153210 A1
- Document ID: US20140153210A1
- Status: Published application
- Kind: A1
- Application number: 13/692,148
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Invensas Corporation
- Applicants: Invensas Corporation
- Inventors: Cyprian Emeka Uzoh
- Web page: https://patentgrep.com/patent/US20140153210A1

## CPC

- B23K 20/023: {Thermo-compression bonding}
- B23K 1/0016: {Soldering of electronic components}
- B23K 20/002: {specially adapted for particular articles or work (B23K20/129 takes precedence)}
- H05K 1/11: Printed elements for providing electric connections to or between printed circuits
- H05K 1/14: Structural association of two or more printed circuits (providing electric connection to or between printed circuits H05K1/11, H01R12/00)
- H05K 1/144: {Stacked arrangements of planar printed circuit boards}
- H05K 1/18: structurally associated with non-printed electric components (H05K1/16 takes precedence)
- H05K 3/0094: {Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement}
- H05K 3/34: by soldering
- H05K 13/046: {Surface mounting (surface mounted components H05K3/341)}
- H05K 13/0465: {by soldering (H05K13/0469 takes precedence)}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 72/071: {Connecting or disconnecting}
- H10W 72/50: Bond wires
- H10W 76/60: Seals
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H05K 1/111: {Pads for surface mounting, e.g. lay-out}
- H05K 2201/04: Assemblies of printed circuits
- H05K 2203/04: Soldering or other types of metallurgic bonding
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01255: {by using masks}
- H10W 72/01335: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01338: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/016: {of strap connectors}
- H10W 72/019: {of bond pads}
- H10W 72/072: {of bump connectors}
- H10W 72/07221: {Aligning}
- H10W 72/07227: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07255: {changes in materials}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07321: {Aligning}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/07341: {Controlling the bonding environment, e.g. atmosphere composition or temperature}
- H10W 72/07355: {changes in materials}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/224: {Bumps having multiple side-by-side cores}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/322: {Multilayered die-attach connectors, e.g. a coating on a top surface of a core}
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/342: {relative to the surface, e.g. recessed, protruding}
- H10W 72/351: {Materials of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- B23K: SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A microelectronic assembly includes a first substrate having a surface and a first conductive element and a second substrate having a surface and a second conductive element. The assembly further includes an electrically conductive alloy mass joined to the first and second conductive elements. First and second materials of the alloy mass each have a melting point lower than a melting point of the alloy. A concentration of the first material varies in concentration from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a first substrate having a surface and a first conductive element;
a second substrate having a surface and a second conductive element; and
an electrically conductive alloy mass joined to the first and second conductive elements, wherein the conductive alloy mass includes a first material, a second material, and a third material, the third material selected to increase the melting point of an alloy including the third material and at least one of the first material or the second material, wherein a concentration of the first material varies from a relatively higher amount at a location disposed toward the first conductive element to a relatively lower amount toward the second conductive element, and wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second conductive element to a relatively lower amount toward the first conductive element.

### Claim 2 (depends on 1)

The assembly of claim 1, wherein at least one of the first or second substrates is of at least one of a semiconductor material or a dielectric material.

### Claim 3 (depends on 1)

The assembly of claim 1, wherein the alloy mass has a thickness of less than five microns.

### Claim 4 (depends on 1)

The assembly of claim 1, wherein the concentration of at least one of the first or second materials varies monotonically from the relatively higher concentration to the relatively lower concentration.

### Claim 5 (depends on 1)

The assembly of claim 1, wherein the third material includes at least one of copper, nickel, tungsten, cobalt, phosphorous, palladium, boron, gold, or silver.

### Claim 6 (depends on 1)

The assembly of claim 1, wherein the location of the relatively higher concentration of the first material is adjacent the first conductive element.

### Claim 7 (depends on 1)

The assembly of claim 1, wherein each of the first and second materials has a melting point of less than 200° Celsius in a state unalloyed with the third material.

### Claim 8 (depends on 7)

The assembly of claim 7, wherein one of the first and second materials has a melting point of less than 50° C.

### Claim 9 (depends on 1)

The assembly of claim 1, wherein the melting point of the alloy formed with the third material and at least one of the first material or the second material has a melting point that is at least 30° C. higher than the melting points of the first and second materials.

### Claim 10 (depends on 1)

The assembly of claim 1, wherein the first material is a different material than the second material and the first and second materials include materials at least one of tin, indium, or gallium.

### Claim 11 (depends on 1)

The assembly of claim 1, wherein the first conductive element includes a bulk conductor mass, the conductive alloy mass overlying the bulk conductor mass, and wherein a portion of the first material is diffused into the bulk conductor mass.

### Claim 12 (depends on 11)

The assembly of claim 11, wherein the first conductive element further includes a barrier layer overlying the bulk conductor mass, the conductive alloy mass bonded to the barrier layer.

### Claim 13 (depends on 1)

The assembly of claim 1, wherein the first substrate includes a first support material layer of at least one of semiconductor or dielectric material, the support material layer defining the surface of the first substrate, and wherein the first conductive element is a metalized via extending through a portion of the first support material layer and being exposed at the first surface.

### Claim 14 (depends on 13)

The assembly of claim 13, wherein a portion of the metalized via is positioned outside the first support material layer.

### Claim 15 (depends on 14)

The assembly of claim 14, wherein the second element includes a second support material of at least one of a semiconductor or dielectric material and layer defining the surface of the second element, wherein the second conductive element is a metalized via extending through a portion of the second support material layer with at least a portion of the second element at the surface, and wherein at least a portion of the conductive alloy mass is disposed within the second support material layer.

### Claim 16 (depends on 1)

The assembly of claim 1, wherein the first and second conductive elements each have widths of less than 25 microns at respective bonding interfaces with the conductive alloy mass.

### Claim 17 (depends on 1)

The assembly of claim 1, wherein the first and second conductive elements each have widths of less than 3 microns at respective bonding interfaces with the conductive alloy mass.

### Claim 18 (depends on 1)

The assembly of claim 1, wherein the first element includes a plurality of first conductive elements, the second element includes a plurality of second conductive elements, and wherein a plurality of conductive alloy masses are joined between respective ones of the first conductive elements and the second conductive elements.

### Claim 19 (depends on 18)

The assembly of claim 18, wherein the first conductive elements each have a width, and wherein the first conductive elements are respectively spaced apart from each other in a lateral direction at a pitch that is less than the width of the first conductive elements.

### Claim 20 (depends on 1)

The assembly of claim 1, wherein the first conductive element includes a plurality of capillary structures extending in a direction towards the second element, the conductive alloy mass surrounding and being joined to at least some individual capillary structures of the plurality of capillary structures.

### Claim 21 (depends on 1)

The microelectronic assembly of claim 1, wherein the first element includes a substrate defining the surface of the first element and extending in lateral directions, the first conductive element being in the form of a post extending away from the surface.

### Claim 22 (depends on 1)

The microelectronic assembly of claim 1, wherein the first element further includes a microelectronic element electrically connected with the first conductive element.

### Claim 23

A microelectronic assembly, comprising:
a first substrate defining a surface and having a first element formed therein;
a second substrate defining a surface and having a second element formed therein; and
an alloy mass joined to the surfaces of the first and second elements, wherein the alloy mass includes first, second, and third materials, wherein a concentration of the first material varies concentration from a relatively higher amount at a location disposed toward the first element to a relatively lower amount toward the second element, wherein a concentration of the second material varies in concentration from a relatively higher amount at a location disposed toward the second element to a relatively lower amount toward the first element, wherein a melting point of the alloy mass is greater than a melting point of the first material in an unalloyed state and greater than a melting point of the second material in an unalloyed state.

### Claim 24 (depends on 23)

The assembly of claim 23, wherein the conductive alloy mass surrounds an internal volume defined between confronting portions of the surfaces of the first and second elements.

### Claim 25 (depends on 24)

The assembly of claim 24, wherein the internal volume is hermetically sealed.

### Claim 26 (depends on 23)

The assembly of claim 23, wherein the first and second elements respectively include first and second conductive elements that define portions of the surface of the first and second elements to which the conductive alloy mass is joined.

### Claim 27

A method for making a microelectronic assembly, including:
aligning a first bond component with a second bond component such that the first and second bond components are in contact with each other, the first bond component being included in a first element having a substrate defining a surface and a first conductive element at the surface, the first bond component including a first material layer adjacent the first conductive element and a first protective layer overlying the first material layer, the second bond component being included in a second element including a substrate defining a surface and a second conductive element exposed at the surface, the second bond component including a second material layer adjacent the second conductive element and a second protective layer overlying the first material layer; and
heating the first and second bond components such that at least portions of the first and second material layers diffuse together to form an alloy mass joining the first and second elements with one another.

### Claim 28 (depends on 27)

The method of claim 27, wherein the heating step is carried out at a first temperature, and wherein the alloy mass has a melting point at a second temperature greater than the first temperature.

### Claim 29 (depends on 27)

The method of claim 27, wherein the first and second protective layers diffuse together and with the first and second material layers during the step of heating to further form the alloy mass.

### Claim 30 (depends on 27)

The method of claim 27, wherein the step of heating is carried out such that a temperature of the first and second bond components reaches between 30° C. and 200° C.

### Claim 31 (depends on 30)

The method of claim 30, wherein after the step of heating, the electrically conductive alloy mass has a melting point of between 200° C. and 800° C.

### Claim 32 (depends on 27)

The method of claim 27, wherein the first material layer includes at least one material component not present in the second material layer before heating.

### Claim 33 (depends on 27)

The method of claim 27, wherein the first and second protective layers are of a similar composition.

### Claim 34 (depends on 27)

The method of claim 27, wherein the first material layer and the second material layer have lower melting points than an alloy formed with the materials from the first and second material layers and the first and second protective layers.

### Claim 35 (depends on 34)

The method of claim 34, wherein the first material is a different material than the second material and the first and second materials include materials at least one of tin, indium, or gallium.

### Claim 36 (depends on 35)

The method of claim 35, wherein the first protective layer includes copper, and wherein the second protective layer includes at least one of copper, nickel, tungsten, cobalt, phosphorous, palladium, boron, gold, or silver.

### Claim 37 (depends on 27)

The method of claim 27, wherein the first conductive element includes a bulk conductor layer and a seed layer that overlies the bulk conductor layer, the first bond component being joined to the seed layer.

### Claim 38 (depends on 37)

The method of claim 37, including controlling a melting point of the first material layer and the first protective layer based upon the thickness of the seed layer.

### Claim 39 (depends on 37)

The method of claim 37, wherein the seed layer includes copper.

### Claim 40 (depends on 37)

The method of claim 37, wherein, during the step of heating, the seed layer also diffuses with the first and second material layers.

### Claim 41 (depends on 37)

The method of claim 37, wherein a portion of the first material layer diffuses into the bulk conductor layer during heating.

### Claim 42 (depends on 37)

The method of claim 37, further comprising providing a barrier layer between the bulk conductor layer and the seed layer, the barrier layer preventing the first material from diffusing into the bulk conductor layer during the heating step.

### Claim 43 (depends on 42)

The method of claim 42, wherein the barrier layer includes at least one of tantalum, tantalum nitride, molybdenum, chromium-molybdenum, nickel, phosphorous, tungsten, cobalt, palladium, titanium nitride, nickel phosphorus, cobalt phosphorus, titanium tungsten, nickel tungsten or combinations thereof.

### Claim 44 (depends on 27)

The method of claim 27, wherein the first substrate is a first support material layer defining the surface of the first element, and wherein the first conductive element is a metalized via extending through a portion of the first support material layer, the method further including forming the first bond component over the metalized via by depositing the first material layer within an opening of a resist layer that overlies the surface of the first element, the opening being aligned with the metalized via.

### Claim 45 (depends on 44)

The method of claim 44, wherein the step of forming the first bond component further includes depositing the first protective layer within the resist layer opening.

### Claim 46 (depends on 44)

The method of claim 44, further comprising:
positioning a seed layer between the surface of the first element and the resist layer prior to depositing the first material layer within the opening and further overlies the end surface of the metalized via,
depositing the first material layer over the seed layer within the opening, and
removing the resist layer and portions of the seed layer that are uncovered by the first material layer.

### Claim 47 (depends on 27)

The method of claim 27, wherein the first substrate is a first support material layer defining the surface of the first element, and wherein the first conductive element is within an opening within the first support material layer, an end surface of the first conductive element and the first bond component being recessed within the opening, and wherein the step of aligning the first bond component with the second bond component includes positioning the second bond component within the opening of the first support material layer.

### Claim 48 (depends on 27)

The method of claim 27, wherein the first substrate is a first support material layer defining the surface of the first element, and wherein the first conductive element is within an opening of the first support material layer opening, an end surface of the first conductive element and the first bond component being recessed within the opening such that an outer surface of the first protective layer is substantially co-planar with the surface of the first support material layer.

### Claim 49

A method for making a microelectronic assembly, including:
aligning a first bond component exposed at a surface of a first element with a second bond component exposed at a surface of a second element such that the first and second bond components are in contact with each other, each of the first and second elements including a substrate, the first bond component including a first material layer and a first protective layer overlying the first material layer, and the second bond component including a second material layer and a second protective layer overlying the second material layer; and
heating the first and second bond components such that at least the first and second material layers diffuse together to form an alloy mass joining the first and second elements with one another, the alloy mass having a melting point higher than melting points of the first and second material layers prior to heating.

### Claim 50 (depends on 49)

The method of claim 49, wherein the first and second protective layers diffuse together and with the first and second material layers during the step of heating to further form the alloy mass.

### Claim 51 (depends on 49)

The method of claim 49, wherein the first bond component surrounds an area of the surface of the first element, wherein the second bond component surrounds an area of the surface of the second element, and wherein aligning the first bond component with the second bond component defines a volume within the first bond component, the second bond component, and the surrounded portions of the surfaces of the first and second elements.

### Claim 52 (depends on 51)

The method of claim 51, wherein the step of heating further causes the internal volume to become hermetically sealed by the conductive alloy mass.

### Claim 53 (depends on 49)

The method of claim 49, wherein the first and second elements respectively include first and second conductive elements that define portions of the surface of the first and second elements to which the bond components are joined, and wherein the step of heating joins the alloy mass between the first and second conductive elements.