# US 2014/0153206 A1 · Systems and methods for embedding devices in printed circuit board structures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0153206 A1 - Document ID: US20140153206A1 - Status: Published application - Kind: A1 - Application number: 13/690,396 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Martin Standing; Andrew Roberts - Web page: https://patentgrep.com/patent/US20140153206A1 ## CPC - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H05K 3/368: {parallel to each other (H05K3/361 takes precedence)} - H10W 70/614: {the multiple chips being integrally enclosed} - H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards - H05K 3/429: {Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers} - H10W 70/611: {for connecting multiple chips together} - H10W 70/685: comprising multiple insulating layers - Y10T 29/49126: Assembling bases - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes. ## Claims ### Claim 1 An insert configured to be embedded in a multi-layer printed circuit board (PCB) that comprises a first layer, a second layer that includes an aperture, and at least a third layer arranged above the second layer, the insert comprising: a semiconductor die arranged at a surface of the insert, wherein the semiconductor die includes at least one pad that is configured to be electrically coupled with to create an electrical connection to at least one circuit of the semiconductor die from external to the semiconductor die; and at least one extender portion that extends a distance along the surface of the insert from the pad to a coupling element with a surface area substantially greater than a surface area of the at least one pad of the semiconductor die, and wherein the coupling element is configured to be electrically coupled with from external to the second layer through an opening in one or more of the first layer and the third layer. ### Claim 2 (depends on 1) The insert of claim 1, wherein the surface area of the coupling element of the insert is at least ten times greater than the surface area of the pad of the semiconductor die. ### Claim 3 (depends on 1) The insert of claim 1, wherein the opening formed in one or more of the first layer and the third layer is formed using mechanical boring. ### Claim 4 (depends on 3) The insert of claim 3, wherein the distance that the extender portion extends from the semiconductor die to the coupling element is selected such that the die is not damaged as a result of forming the opening using the mechanical boring. ### Claim 5 (depends on 1) The insert of claim 1, wherein the insert comprises at least one alignment portion that interfaces with a corresponding alignment portion of the aperture in the second layer to align the insert within the aperture. ### Claim 6 A printed circuit board (PCB) comprising: a first layer; a second layer that includes an aperture, wherein the aperture is sized, shaped, and arranged to receive an insert that is configured to be disposed in the aperture in the second layer, wherein the insert comprises: a semiconductor die arranged at a surface of the insert, wherein the semiconductor die includes at least one pad that is configured to be electrically coupled with to create an electrical connection to at least one circuit of the semiconductor die from external to the semiconductor die, and at least one extender portion that extends a distance spaced apart along the surface of the insert from the pad to a coupling element with a surface area substantially greater than a surface area of the at least one pad of the semiconductor die; and wherein the PCB further comprises at least one third layer arranged upon the second layer to substantially enclose the semiconductor die within the aperture; and wherein the coupling element is configured to be electrically coupled to from external to the second layer through an opening formed in one or more of the first layer and the third layer. ### Claim 7 (depends on 6) The PCB of claim 6, wherein the surface area of the coupling element of the insert is at least ten times greater than the surface area of the pad of the semiconductor die. ### Claim 8 (depends on 6) The PCB of claim 6, wherein the opening formed in one or more of the first layer and the third layer is formed using mechanical boring. ### Claim 9 (depends on 8) The PCB of claim 8, wherein the distance that the extender portion extends from the semiconductor die to the coupling element is selected such that the die is not damaged as a result of forming the opening using the mechanical boring. ### Claim 10 (depends on 6) The PCB of claim 6, wherein the insert comprises at least one alignment portion that interfaces with a corresponding alignment portion of the aperture in the second layer to align the insert within the aperture. ### Claim 11 A printed circuit board (PCB) comprising: a plurality of layers coupled to form a stack, wherein at least one layer of the plurality of layers comprises an aperture; an insert comprising a die and at least one coupling element spaced apart from the die, the insert configured to be disposed in the aperture; and at least one via formed through the plurality of layers and the at least one coupling element to electrically couple the insert with at least one of the plurality of layers other than the at least one layer comprising the aperture. ### Claim 12 (depends on 11) The PCB of claim 11, wherein the die comprises an active element. ### Claim 13 (depends on 12) The PCB of claim 12, wherein the active element comprises an integrated circuit (IC) device. ### Claim 14 (depends on 13) The PCB of claim 13, wherein the IC device comprises at least one of a power IC, a control IC, a memory IC or an inverter IC. ### Claim 15 (depends on 11) The PCB of claim 11, wherein at least one of the plurality of layers comprises pre-preg. ### Claim 16 (depends on 11) The PCB of claim 11, wherein at least one of the plurality of layers comprises a dual-sided core. ### Claim 17 (depends on 1) The PCB of claim 1, wherein the insert comprises a plurality of layers. ### Claim 18 (depends on 17) The PCB of claim 17, wherein the insert comprises a different number of layers than the at least one layer of the plurality of layers comprising the aperture. ### Claim 19 (depends on 11) The PCB of claim 11, wherein the at least one via comprises a plated through-hole via. ### Claim 20 (depends on 11) The PCB of claim 11, wherein the at least one via is formed through the plurality of layers and the at least one coupling element to electrically couple the insert with at least one of the plurality of layers other than the at least one layer comprising the aperture and with the layer comprising the aperture. ### Claim 21 A method of forming a printed circuit board (PCB) stack comprising: forming an insert comprising a semiconductor die arranged at a surface of the insert, wherein the semiconductor die includes at least one pad that is configured to be electrically coupled with to create an electrical connection to at least one circuit of the semiconductor die from external to the semiconductor die, and at least one extender portion that extends a distance along the surface of the insert from the pad to a coupling element with a surface area substantially greater than a surface area of the at least one pad of the semiconductor die; forming a first layer comprising an aperture; arranging the insert in the aperture; arranging at least one additional layer with the first layer to form a stack; and electrically coupling with the coupling element of the insert from external to the first layer of the stack through an opening in one or more of the at least one additional layers. ### Claim 22 (depends on 21) The method of claim 21, wherein the first layer comprises a plurality of layers. ### Claim 23 (depends on 22) The method of claim 22, wherein the die comprises an integrated circuit (IC). ### Claim 24 (depends on 22) The method of claim 22, wherein arranging at least one additional layer adjacent the first layer comprises laminating the at least one additional layer to the first layer. ### Claim 25 (depends on 21) The method of claim 21, further comprising forming the opening by mechanical boring. ### Claim 26 (depends on 25) The method of claim 25, wherein the distance that the extender portion extends from the semiconductor die to the coupling element is selected such that the die is not damaged as a result of forming the opening using the mechanical boring. ### Claim 27 (depends on 21) The method of claim 21, wherein forming the insert further comprises forming at least one alignment portion on the insert that interfaces with a corresponding alignment portion of the aperture to align the insert within the aperture.