# US 2014/0152938 A1 · Liquid crystal display and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152938 A1 - Document ID: US20140152938A1 - Status: Published application - Kind: A1 - Application number: 13/865,326 - Filed: 2013-04-18 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Minjic LEE; Seeung LEE; Byunghyun LEE - Web page: https://patentgrep.com/patent/US20140152938A1 ## CPC - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G02F 1/13456: {Cell terminals located on one side of the display only} - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G09G 3/3614: {Control of polarity reversal in general} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes - G09G 2310/0281: Arrangement of scan or data electrode driver circuits at the periphery of a panel not inherent to a split matrix structure - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A liquid crystal display and a method for manufacturing the same capable of reducing a bezel are disclosed. The liquid crystal display includes a display panel including vertical lines, horizontal lines, and pixels and a driver integrated circuit (IC) supplying a data voltage and a gate pulse to the pixels through the vertical lines. The vertical lines include vertical data lines to which the data voltage is supplied, vertical gate lines to which the gate pulse is supplied, and vertical common voltage lines to which a common voltage is supplied. The horizontal lines include horizontal gate lines which are connected to the vertical gate lines and receive the gate pulse through the vertical gate lines. ## Claims ### Claim 1 A liquid crystal display comprising: a display panel including vertical lines, horizontal lines, and pixels; and a driver integrated circuit (IC) configured to supply a data voltage and a gate pulse to the pixels through the vertical lines, wherein the vertical lines include vertical data lines to which the data voltage is supplied, vertical gate lines to which the gate pulse is supplied, and vertical common voltage lines to which a common voltage is supplied, wherein the horizontal lines include horizontal gate lines which are connected to the vertical gate lines and receive the gate pulse through the vertical gate lines. ### Claim 2 (depends on 1) The liquid crystal display of claim 1, wherein one vertical line is positioned between the horizontally adjacent pixels of the display panel. ### Claim 3 (depends on 2) The liquid crystal display of claim 2, wherein when the number of pixels positioned on one line of the display panel is ‘m’, where m is a positive integer equal to or greater than 2, the number of vertical lines is ‘m’, wherein when the number of vertical lines and the number of horizontal lines in the display panel are ‘m’ and ‘n’, respectively, where n is a positive integer equal to or greater than 2, a resolution of a pixel array of the display panel is ‘m*n/2’. ### Claim 4 (depends on 2) The liquid crystal display of claim 2, wherein the driver IC includes: a source driver IC configured to output the data voltage; and a gate driver IC configured to output the gate pulse, wherein both the source driver IC and the gate driver IC are mounted on a chip-on film (COF). ### Claim 5 (depends on 4) The liquid crystal display of claim 4, wherein the source driver IC supplies the data voltage of a first polarity to the odd-numbered vertical data lines and supplies the data voltage of a second polarity to the even-numbered vertical data lines during one frame period, wherein the data voltage supplied to each of the vertical data lines is maintained in one polarity during one frame period. ### Claim 6 (depends on 2) The liquid crystal display of claim 2, wherein connection portions between the vertical gate lines and the horizontal gate lines are positioned close to the middle of the display panel as the connection portions are far away from the driver IC. ### Claim 7 (depends on 6) The liquid crystal display of claim 6, wherein the connection portions between the vertical gate lines and the horizontal gate lines have a V-shape in the display panel. ### Claim 8 (depends on 2) The liquid crystal display of claim 2, wherein the horizontal lines are formed using gate metal patterns formed on a substrate of the display panel, wherein semiconductor patterns and source-drain metal patterns positioned on the gate metal patterns are stacked to form the vertical lines, wherein a gate insulating layer is formed between the vertical lines and the horizontal lines. ### Claim 9 (depends on 8) The liquid crystal display of claim 8, wherein a first passivation layer and an organic protection layer are stacked on the vertical lines and the gate insulating layer, wherein a common electrode and a link pattern of the pixels formed of a transparent conductive material are formed on the organic protection layer, wherein a second passivation layer is formed on the common electrode and the link pattern, wherein pixel electrodes of the pixels is formed on the second passivation layer, wherein the link pattern connects the vertical gate line to the horizontal gate line through a contact hole, which passes through the organic protection layer and the first passivation layer and exposes the vertical gate line, and a contact hole, which passes through the organic protection layer, the first passivation layer, and the gate insulating layer and exposes the horizontal gate line. ### Claim 10 (depends on 2) The liquid crystal display of claim 2, wherein a common voltage line to which the common voltage is supplied, and a ground line to which a ground level voltage is supplied, are formed in a bezel area outside a formation area of a pixel array including the pixels in the display panel. ### Claim 11 (depends on 10) The liquid crystal display of claim 10, wherein a width of the bezel area in the display panel is equal to or less than about 1.0 mm. ### Claim 12 A method for manufacturing a liquid crystal display comprising: forming vertical lines and horizontal lines crossing the vertical lines on a substrate and forming a plurality of pixels on the substrate to manufacture a display panel; and connecting a driver integrated circuit (IC), which supplies a data voltage and a gate pulse to the pixels through the vertical lines, to the display panel, wherein the vertical lines include vertical data lines to which the data voltage is supplied, vertical gate lines to which the gate pulse is supplied, and vertical common voltage lines to which a common voltage is supplied, wherein the horizontal lines include horizontal gate lines which are connected to the vertical gate lines and receive the gate pulse through the vertical gate lines. ### Claim 13 (depends on 12) The method of claim 12, wherein one vertical line is positioned between the horizontally adjacent pixels of the display panel. ### Claim 14 (depends on 13) The method of claim 13, wherein the manufacturing of the display panel further includes forming a common voltage line to which the common voltage is supplied, and a ground line to which a ground level voltage is supplied, in a bezel area outside a formation area of a pixel array including the pixels. ### Claim 15 (depends on 14) The method of claim 14, wherein a width of the bezel area in the display panel is equal to or less than about 1.0 mm. ### Claim 16 A method for manufacturing a liquid crystal display including a display panel including vertical lines, horizontal lines, and pixels and a driver integrated circuit (IC) supplying a data voltage and a gate pulse to the pixels through the vertical lines, the method comprising: forming the horizontal lines using gate metal patterns formed on a substrate of the display panel; forming a gate insulating layer on the substrate to cover the horizontal lines; stacking semiconductor patterns and source-drain metal patterns on the gate insulating layer to form the vertical lines; stacking a first passivation layer and an organic protection layer on the vertical lines and the gate insulating layer; forming a common electrode and a link pattern of the pixels formed of a transparent conductive material on the organic protection layer; forming a second passivation layer on the common electrode and the link pattern; and forming pixel electrodes of the pixels on the second passivation layer, wherein the vertical lines include vertical data lines to which the data voltage is supplied, vertical gate lines to which the gate pulse is supplied, and vertical common voltage lines to which a common voltage is supplied, wherein the horizontal lines include horizontal gate lines which are connected to the vertical gate lines and receive the gate pulse through the vertical gate lines. ### Claim 17 (depends on 16) The method of claim 16, wherein one vertical line is positioned between the horizontally adjacent pixels of the display panel. ### Claim 18 (depends on 17) The method of claim 17, wherein the link pattern connects the vertical gate line to the horizontal gate line through a contact hole, which passes through the organic protection layer and the first passivation layer and exposes the vertical gate line, and a contact hole, which passes through the organic protection layer, the first passivation layer, and the gate insulating layer and exposes the horizontal gate line. ### Claim 19 (depends on 17) The method of claim 17, wherein when the number of pixels positioned on one line of the display panel is ‘m’, where m is a positive integer equal to or greater than 2, the number of vertical lines is ‘m’, wherein when the number of vertical lines and the number of horizontal lines in the display panel are ‘m’ and ‘n’, respectively, where n is a positive integer equal to or greater than 2, a resolution of a pixel array of the display panel is ‘m*n/2’. ### Claim 20 (depends on 17) The method of claim 17, wherein connection portions between the vertical gate lines and the horizontal gate lines are positioned close to the middle of the display panel as the connection portions are far away from the driver IC.