# US 2014/0152935 A1 · Flat display panel having narrow bezel

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- Number: US 2014/0152935 A1
- Document ID: US20140152935A1
- Status: Published application
- Kind: A1
- Application number: 14/082,022
- Filed: 2013-11-15
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: LG Display Co., Ltd.
- Applicants: LG Display Co., Ltd.
- Inventors: Seungho Heo; Byeongseong So
- Web page: https://patentgrep.com/patent/US20140152935A1

## CPC

- G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)}
- G02F 1/1339: Gaskets; Spacers; Sealing of cells
- G02F 1/134372: {for fringe field switching [FFS] where the common electrode is not patterned}
- G02F 2201/121: common or background
- G02F 2202/16: conductive
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

The present disclosure relates to reducing bezel area of a flat display panel comprising a substrate with a non-display area surrounding a display area, the display area comprising common lines coupled to corresponding rows of pixels; and a gate driver formed in the non-display area. The display may further include a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to the rows of pixels. Alternatively, the display may further include a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from top to bottom of the non-display area and coupled to said common lines to apply a common voltage.

## Claims

### Claim 1

A flat display panel, comprising:
a substrate including a display area and a non-display area surrounding the display area, the display area comprising a plurality of common lines each coupled to a corresponding one of a plurality of rows of pixels;
a gate driver formed in the non-display area;
a conductive sealing region formed in the non-display area and configured to supply a common line voltage; and
a plurality of common pads formed within the conductive sealing region and each coupled to a corresponding one of the common lines to apply a common line voltage to said corresponding one of the rows of pixels.

### Claim 2 (depends on 1)

The flat display panel according to claim 1, wherein the display area comprises a plurality of gate lines each coupled to said corresponding one of the rows of pixels, and wherein the gate driver formed in the non-display area between the display area and the conductive sealing region is configured to apply gate signals to the gate lines.

### Claim 3 (depends on 1)

The flat display panel according to claim 1, wherein said gate lines are substantially parallel to said common lines within the display area.

### Claim 4 (depends on 1)

The flat display panel according to claim 1, wherein the common pads and conductive sealing material disposed in the conductive sealing region directly contact each other to make an electric connection.

### Claim 5 (depends on 1)

The flat display panel according to claim 1, wherein the common pads are electrically connected to common pad terminals via contact holes formed in an insulating layer disposed to cover the common pads.

### Claim 6 (depends on 1)

The flat display panel according to claim 1, wherein conductive sealing material disposed in the conductive sealing region electrically contacting said common pads receives the common line voltage from a data driver disposed on an upper edge of the display panel.

### Claim 7 (depends on 1)

The flat display panel according to claim 1, wherein a minimum width of a bezel of the flat display panel corresponds to a minimum width of space for the gate driver and a minimum width of space for the conductive sealing region formed within the non-display area.

### Claim 8

A flat display panel, the flat panel display comprising:
a substrate including a display area and a non-display area surrounding the display area, the display area comprising a plurality of common lines each coupled to a corresponding one of a plurality of horizontal rows of pixels;
a gate driver formed in the non-display area;
a vertical common line formed in the non-display area between the gate driver and the display area, the vertical common line extending from a top of the non-display area to a bottom of the non-display and coupled to said common lines to apply a common voltage.

### Claim 9 (depends on 8)

The flat display panel according to claim 8, wherein the gate driver formed in the non-display area is configured to apply gate signals to a plurality of gate lines extending through a region of the vertical common line to the display area, said gate lines each coupled to said corresponding one of the rows of pixels.

### Claim 10 (depends on 8)

The flat display panel according to claim 8, wherein said gate lines are substantially parallel to said common lines.

### Claim 11 (depends on 8)

The flat display panel according to claim 8, further comprising sealing material formed in the non-display area and surrounding the gate driver and the plurality of pixels.

### Claim 12 (depends on 11)

The flat display panel according to claim 11, wherein a minimum width of a bezel of the flat display panel corresponds to a minimum width of space for the gate driver, a minimum width of space for the vertical common line, and a minimum width of space for the sealing material formed within the non-display area.