# US 2014/0152629 A1 · Shift register and flat panel display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152629 A1 - Document ID: US20140152629A1 - Status: Published application - Kind: A1 - Application number: 14/082,682 - Filed: 2013-11-18 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: LG Display Co., Ltd. - Applicants: LG Display Co., Ltd. - Inventors: Byeong-Seong SO; Seung-Ho HEO; JoungMi CHOI - Web page: https://patentgrep.com/patent/US20140152629A1 ## CPC - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G11C: STATIC STORES (semiconductor memory devices H10B) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract Disclosed are a shift register and a flat panel display device. The shift register includes a plurality of stages that supply a gate-on voltage pulse to a plurality of gate lines formed in a display panel. Each of the stages includes a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node, a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node, a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal, and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines using the clock signal. ## Claims ### Claim 1 A shift register comprising a plurality of stages configured to supply a gate-on voltage pulse to a plurality of gate lines which are formed in a display panel, each of the plurality of stages comprising: a pull-up transistor configured to supply one of a plurality of clock signals to an output node according to a voltage of a first node; a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node; a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal; and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines by using the clock signal supplied to the output node, respectively. ### Claim 2 (depends on 1) The shift register of claim 1, wherein the switching unit is turned on according to voltages of first and second nodes of a previous stage, and adjusts a falling time of the clock signal to supply a first gate-on voltage pulse to a first gate line of the two adjacent gate lines and to simultaneously bypass the clock signal to a second gate line of the two adjacent gate lines. ### Claim 3 (depends on 2) The shift register of claim 2, wherein the first gate-on voltage pulse has a pulse width narrower than the clock signal, and wherein the second gate-on voltage pulse has the same pulse width as the clock signal to overlap the first gate-on voltage pulse. ### Claim 4 (depends on 2) The shift register of claim 2, wherein the switching unit comprises: a first switching transistor configured to turn on according to the voltage of the first node of the previous stage to supply the clock signal, supplied from the output node, to the first gate line; a second switching transistor configured to turn on according to the voltage of the second node of the previous stage to supply the gate-off voltage to the first gate line; and a bypass line connected to the output node and the second gate line, and configured to bypass the clock signal, supplied from the output node, to the second gate line. ### Claim 5 (depends on 4) The shift register of claim 4, wherein the first gate-on voltage pulse has a pulse width narrower than the clock signal according to the first and second switching transistors being turned on. ### Claim 6 (depends on 2) The shift register of claim 2, further comprising a sharing line formed in correspondence with two adjacent stages, and configured to enable a second node of each of the two adjacent stages to be shared. ### Claim 7 (depends on 2) The shift register of claim 2, wherein, the second node comprises an odd-numbered second node and an even-numbered second node, the pull-down transistor comprises: a first pull-down transistor configured to supply the gate-off voltage to the output node according to a voltage of the odd-numbered second node; and a second pull-down transistor configured to supply the gate-off voltage to the output node according to a voltage of the even-numbered second node, and the node controller alternately controls the voltage of the odd-numbered second node and the voltage of the even-numbered second node such that the first and second pull-down transistors are alternately turned on. ### Claim 8 (depends on 7) The shift register of claim 7, wherein the switching unit comprises: a first switching transistor configured to turn on according to the voltage of the first node of the previous stage to supply the clock signal, supplied from the output node, to the first gate line; a second switching transistor configured to turn on according to a voltage of an odd-numbered second node of the previous stage to supply the gate-off voltage to the first gate line; a third switching transistor configured to turn on according to a voltage of an even-numbered second node of the previous stage to supply the gate-off voltage to the first gate line; and a bypass line connected to the output node and the second gate line, and configured to bypass the clock signal, supplied from the output node, to the second gate line. ### Claim 9 (depends on 7) The shift register of claim 7, further comprising first and second sharing lines formed in correspondence with two adjacent stages, and configured to enable an odd-numbered second node and even-numbered second node of each of the two adjacent stages to be shared. ### Claim 10 A flat panel display device comprising: a display panel configured to comprise an active area, comprising a plurality of pixels that are respectively formed in a plurality of pixel areas defined by intersections between a plurality of gate lines and a plurality of data lines, and an inactive area defined near the active area; a plurality of data drivers configured to convert input pixel data into data signals, and respectively supply the data signals to the plurality of data lines; a gate driver provided in the inactive area of the display panel in connection with the plurality of gate lines, and configured to generate a gate-on voltage pulse on the basis of a gate start signal and a plurality of clock signals to supply the gate-on voltage pulse to the plurality of gate lines; and a timing controller configured to convert input video data into the pixel data, supply the pixel data to the plurality of data drivers, and supply a gate control signal, comprising the gate start signal and the plurality of clock signals, to the gate driver, wherein the gate driver includes a shift register comprising: a pull-up transistor configured to supply one of the plurality of clock signals to an output node according to a voltage of a first node; a pull-down transistor configured to supply a gate-off voltage to the output node according to a voltage of a second node; a node controller configured to control the voltages of the first and second nodes on the basis of a gate start signal; and a switching unit connected to at least two gate lines adjacent to the output node, and configured to sequentially supply gate-on voltage pulses having different pulse widths to the at least two adjacent gate lines by using the clock signal supplied to the output node, respectively. ### Claim 11 (depends on 10) The flat panel display device of claim 10, wherein the switching unit is turned on according to voltages of first and second nodes of a previous stage, and adjusts a falling time of the clock signal to supply a first gate-on voltage pulse to a first gate line of the two adjacent gate lines and to simultaneously bypass the clock signal to a second gate line of the two adjacent gate lines. ### Claim 12 (depends on 11) The flat panel display device of claim 11, wherein, the first gate-on voltage pulse has a pulse width narrower than the clock signal, and the second gate-on voltage pulse has the same pulse width as the clock signal to overlap the first gate-on voltage pulse. ### Claim 13 (depends on 11) The flat panel display device of claim 11, wherein the switching unit comprises: a first switching transistor configured to turn on according to the voltage of the first node of the previous stage to supply the clock signal, supplied from the output node, to the first gate line; a second switching transistor configured to turn on according to the voltage of the second node of the previous stage to supply the gate-off voltage to the first gate line; and a bypass line connected to the output node and the second gate line, and configured to bypass the clock signal, supplied from the output node, to the second gate line. ### Claim 14 (depends on 13) The flat panel display device of claim 13, wherein the first gate-on voltage pulse has a pulse width narrower than the clock signal according to the first and second switching transistors being turned on. ### Claim 15 (depends on 11) The flat panel display device of claim 11, wherein the shift register further comprises a sharing line formed in correspondence with two adjacent stages, and configured to enable a second node of each of the two adjacent stages to be shared. ### Claim 16 (depends on 11) The flat panel display device of claim 11, wherein, the second node comprises an odd-numbered second node and an even-numbered second node, the pull-down transistor comprises: a first pull-down transistor configured to supply the gate-off voltage to the output node according to a voltage of the odd-numbered second node; and a second pull-down transistor configured to supply the gate-off voltage to the output node according to a voltage of the even-numbered second node, and the node controller alternately controls the voltage of the odd-numbered second node and the voltage of the even-numbered second node such that the first and second pull-down transistors are alternately turned on. ### Claim 17 (depends on 16) The flat panel display device of claim 16, wherein the switching unit comprises: a first switching transistor configured to turn on according to the voltage of the first node of the previous stage to supply the clock signal, supplied from the output node, to the first gate line; a second switching transistor configured to turn on according to a voltage of an odd-numbered second node of the previous stage to supply the gate-off voltage to the first gate line; a third switching transistor configured to turn on according to a voltage of an even-numbered second node of the previous stage to supply the gate-off voltage to the first gate line; and a bypass line connected to the output node and the second gate line, and configured to bypass the clock signal, supplied from the output node, to the second gate line. ### Claim 18 (depends on 16) The flat panel display device of claim 16, wherein the shift register further comprises first and second sharing lines formed in correspondence with two adjacent stages, and configured to enable an odd-numbered second node and even-numbered second node of each of the two adjacent stages to be shared.