# US 2014/0152478 A1 · Randomized time-interleaved sample-and-hold system

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- Number: US 2014/0152478 A1
- Document ID: US20140152478A1
- Status: Published application
- Kind: A1
- Application number: 13/751,062
- Filed: 2013-01-26
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Crest Semiconductors, Inc.
- Applicants: Crest Semiconductors, Inc.
- Inventors: Donald E. Lewis; Ryan James Kier; Rex K. Hales; Yusuf A. Haque
- Web page: https://patentgrep.com/patent/US20140152478A1

## CPC

- H03M 1/0673: {using random selection of the elements (with data-controlled random generator H03M1/0665)}
- H03M 1/1215: {using time-division multiplexing}
- H03M 1/168: {and delivering the same number of bits}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

## Claims

### Claim 1

A time interleaving Analog-to-Digital Converter (ADC), comprising:
a plurality of ADCs;
a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and
a random number generator to pseudo randomly select which ADC samples the input signal; and
a circuit for adjusting the bandwidth of the plurality of ADCs.

### Claim 2 (depends on 1)

The time interleaving ADC of claim 1, wherein the time interleaving ADCs adjusts bandwidth, timing, offset and gain mismatches by using mismatch adjustment coefficients determined by a mathematical function.

### Claim 3 (depends on 2)

The time interleaving ADC of claim 2, wherein the time interleaving ADCs are pipelined ADCs.

### Claim 4 (depends on 1)

The time interleaving ADC of claim 1, further comprising at least three ADCs when increasing the sample rate by two times; and once one ADC is sampled, the next ADC to be sampled is pseudo randomly selected from the two remaining ADCs.

### Claim 5 (depends on 1)

The time interleaving ADC of claim 1, wherein the first interleaved stage of a multistage ADC is pseudo randomly sampled.

### Claim 6 (depends on 1)

The time interleaving ADC of claim 1, further comprising a controller to randomly select one of N samplings paths for sampling the input signal and gating the outputs of N interleaved samplers to select only one output corresponding to the randomly selected sampled path.

### Claim 7 (depends on 1)

The time interleaving ADC of claim 1, wherein each of the interleaved ADCs comprises:
an input to receive an input signal;
a first filter connected to the input signal, the output of the first filter connected to a quantizer means to sample the signal received by the quantizer; and
a second filter connected to the input signal, with the output of the second filter connected to a residue generator;
such residue generator coupled to said quantizer and a sample-and-hold circuit;
in which the sample-and-hold circuit samples the signal received by the residue generator separately from the quantizer path; and
in which the sample and hold in both paths have adjustable bandwidth.

### Claim 8 (depends on 7)

The time interleaving ADC of claim 7, in which the input is connected to said first filter with said adjustable bandwidth and the output of said first filter is connected to the sample-and-hold circuit.

### Claim 9 (depends on 8)

The time interleaving ADC of claim 8, wherein said sample and holds do not have adjustable bandwidth.

### Claim 10 (depends on 1)

The time interleaving ADC of claim 1, in which the timing adjustment includes time increments smaller than smallest delay created by the clock adjustment circuitry when applied to the ADC.

### Claim 11 (depends on 10)

The time interleaving ADC of claim 10, wherein time modulation of said time adjusted values from said clock adjustment circuitry is used to create smaller time increment values.

### Claim 12 (depends on 11)

The time interleaving ADC of claim 11, wherein said time modulation is pseudorandom with programmable average delay values.

### Claim 13 (depends on 1)

The time interleaving ADC of claim 1, wherein multiple sample and hold circuits use a common sampling switch.

### Claim 14 (depends on 7)

The time interleaving ADC of claim 7, wherein multiple sample and hold circuits use a common sampling switch

### Claim 15 (depends on 7)

The time interleaving ADC of claim 7, wherein at least N−1 of said sample-and-hold circuits adjusts the bandwidth for at least N of said time interleaved ADCs.

### Claim 16 (depends on 8)

The time interleaving ADC of claim 8, further comprising a digital multiplexor to combine outputs from the individual ADC's into a single, time-interleaved output stream.

### Claim 17 (depends on 1)

The time interleaving ADC of claim 1, wherein an actual delay adjustment achieved in the sampling time of the ADCs is less than a delay adjustment in a corresponding clocking waveform made by said timing adjustment circuit.

### Claim 18 (depends on 1)

The time-interleaving ADC of claim 1, further comprising:
memory to store a bandwidth coefficient for each of said ADCs; and
a bandwidth adjusting component to use the bandwidth coefficient stored in said memory to alter the bandwidth of the ADCs in the analog domain.

### Claim 19 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store a gain adjustment value for each of the ADCs; and
a gain adjusting component to minimize gain error between each ADC using a gain adjustment value.

### Claim 20 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store an offset adjustment value for each of the ADCs; and
an offset adjusting component to minimize offset mismatch between each ADC using the offset adjustment value.

### Claim 21 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store a gain coefficient, gain adjustment value for each of the ADCs; and
a gain adjusting component to modify a digital output value of each of the ADCs to equalize a gain for each path through the time-interleaving ADCs using the gain coefficient values stored in the memory.

### Claim 22 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store an offset coefficient for each of the ADCs; and
an offset adjusting component to modify a digital output value of each of the ADCs such that the ADCs match an offset between an analog input and an output for each path through the time-interleaving ADCs using the offset coefficient values stored in the memory.

### Claim 23 (depends on 1)

The time interleaving ADC of claim 1, wherein bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch are minimized using a correction coefficient that adjusts a bandwidth, sample time delay, gain, and offset mismatch for each path through the time-interleaving ADC.

### Claim 24 (depends on 23)

The time interleaving ADC of claim 23, further comprising a function that uses output data from Fast Fourier Transformation (FFT) of said ADC outputs at multiple input frequencies to determine said bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch such that said correction coefficients suitable for input into digital memory of said time-interleaving ADC are obtained.

### Claim 25

A method for operating a time interleaving Analog-to-Digital Converter (ADC), said time interleaving Analog-to-Digital Converter comprising:
a plurality of ADCs;
a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a random number generator; and
a timing adjustment circuit;
said method comprising, with said timing adjustment circuit:
receiving and adjusting the clock signals before the clock signals are received by the plurality of ADCs; and
adjusting a bandwidth of the plurality of ADCs.

### Claim 26 (depends on 25)

The method of claim 25, further comprising equally spacing said samplings of said input signal in time by operation of said timing adjustment circuit.

### Claim 27 (depends on 25)

The method of claim 25, further comprising adjusting a bandwidth of each of the plurality of ADCs individually.

### Claim 28 (depends on 25)

The method of claim 25, further comprising adjusting a gain of a digital output value of each of the plurality of ADCs.

### Claim 29 (depends on 25)

The method of claim 25, further comprising adjusting an offset of a digital output value of each path through the time-interleaved ADC using an offset coefficient to match an offset of an analog input and an output for each path through the time-interleaved ADC.

### Claim 30 (depends on 29)

The method of claim 29, further comprising adjusting a gain of a digital output value of each path through the time-interleaved ADC using gain coefficient to match gain offset between an analog input and an output for each path through the time-interleaved ADC.

### Claim 31 (depends on 30)

The method of claim 30, further comprising minimizing each of bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch using correction coefficients that adjusts the bandwidth, sample time delay, gain, and offset mismatch for each path through one of the ADCs.

### Claim 32 (depends on 31)

The method of claim 31, further comprising determining the bandwidth mismatch, sample time mismatch, gain mismatch and offset mismatch of individual ADC's by employing Fast Fourier Transforms (FFTs j on data collected from operation of the time interleaving Analog-to-Digital Converter at a number of frequencies.

### Claim 33

A time interleaving Analog-to-Digital Converter (ADC), comprising:
a plurality of ADCs;
a timing generator which generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a random number generator to pseudo randomly select which ADC samples the input signal; and
a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate and time adjustment values;
in which the timing adjustment includes time increments smaller than smallest delay created by the clock adjustment circuitry when applied to the ADC.