# US 2014/0152477 A1 · Time Interleaving Analog-to-Digital Converter

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- Number: US 2014/0152477 A1
- Document ID: US20140152477A1
- Status: Published application
- Kind: A1
- Application number: 13/706,035
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Crest Semiconductors, Inc.
- Applicants: Crest Semiconductors, Inc.
- Inventors: Donald E. Lewis; Ryan James Kier; Rex K. Hales; Yusuf Haque
- Web page: https://patentgrep.com/patent/US20140152477A1

## CPC

- H03M 1/1061: {using digitally programmable trimming circuits}
- H03M 1/1245: {Details of sampling arrangements or methods}
- H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

## Claims

### Claim 1

A time interleaving Analog-to-Digital Converter (ADC), comprising:
a plurality of ADCs;
a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate, and
a circuit for adjusting the bandwidth of the plurality of ADCs.

### Claim 2 (depends on 1)

The time interleaving ADC of claim 1, wherein each of the interleaved ADCs comprises:
an input to receive an input signal;
a first filter connected to the input signal, the output of the first filter connected to a quantizer means to sample the signal received by the quantizer; and
a second filter connected to the input signal, with the output of the second filter connected to a residue generator;
such residue generator coupled to said quantizer and a sample-and-hold circuit;
in which the sample-and-hold circuit samples the signal received by the residue generator separately from the quantizer path; and
in which the sample and hold in both paths have adjustable bandwidth.

### Claim 3 (depends on 2)

The time interleaving ADC of claim 2, in which the input is connected to said first filter with said adjustable bandwidth and the output of said first filter is connected to the sample-and-hold circuit.

### Claim 4 (depends on 3)

The time interleaving ADC of claim 3, wherein said sample and holds do not have adjustable bandwidth.

### Claim 5 (depends on 1)

The time interleaving ADC of claim 1, in which the timing adjustment includes time increments smaller than smallest delay created by the clock adjustment circuitry when applied to the ADC.

### Claim 6 (depends on 5)

The time interleaving ADC of claim 5, wherein time modulation of said time adjusted values from said clock adjustment circuitry is used to create smaller time increment values.

### Claim 7 (depends on 6)

The time interleaving ADC of claim 6, wherein said time modulation is pseudorandom with programmable average delay values.

### Claim 8 (depends on 5)

The time interleaving ADC of claim 5, wherein jitter in the clock used to delay the timing of an ADC with respect to other ADCs is reduced by adjusting the timing of the clock signals before the clock signals are received by the ADCs.

### Claim 9 (depends on 1)

The time interleaving ADC of claim 1, wherein jitter in said clock used to delay said timing of an ADC with respect to other ADCs is reduced by adjusting the timing of the clock signals before the clock signals are received by the ADCs.

### Claim 10 (depends on 2)

The time interleaving ADC of claim 2, wherein at least N-1 of said sample-and-hold circuits adjusts the bandwidth for at least N of said interleaved ADCs.

### Claim 11 (depends on 5)

The time interleaving ADC of claim 5, further comprising a digital multiplexor to combine outputs from the individual ADC's into a single, time-interleaved output stream.

### Claim 12 (depends on 1)

The time interleaving ADC of claim 1, wherein an actual delay adjustment achieved in the sampling time of the ADCs is less than a delay adjustment in a corresponding clocking waveform made by said timing adjustment circuit.

### Claim 13 (depends on 1)

The time-interleaving ADC of claim 1, further comprising:
memory to store a bandwidth coefficient for each of said ADCs; and
a bandwidth adjusting component to use the bandwidth coefficient stored in said memory to alter the bandwidth of the ADCs in the analog domain.

### Claim 14 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store a gain adjustment value for each of the ADCs; and
a gain adjusting component to minimize gain error between each ADC using a gain adjustment value.

### Claim 15 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store an offset adjustment value for each of the ADCs; and
an offset adjusting component to minimize offset mismatch between each ADC using the offset adjustment value.

### Claim 16 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store a gain coefficient, gain adjustment value for each of the ADCs; and
a gain adjusting component to modify a digital output value of each of the ADCs to equalize a gain for each path through the time-interleaving ADCs using the gain coefficient values stored in the memory.

### Claim 17 (depends on 1)

The time interleaving ADC of claim 1, further comprising:
memory to store an offset coefficient for each of the ADCs; and
an offset adjusting component to modify a digital output value of each of the ADCs such that the ADCs match an offset between an analog input and an output for each path through the time-interleaving ADCs using the offset coefficient values stored in the memory.

### Claim 18 (depends on 1)

The time interleaving ADC of claim 1, wherein bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch are minimized using a correction coefficient that adjusts a bandwidth, sample time delay, gain, and offset mismatch for each path through the time-interleaving ADC.

### Claim 19 (depends on 18)

The time interleaving ADC of claim 18, further comprising an algorithm that uses output data from Fast Fourier Transformation (FFT) of said ADC outputs at multiple input frequencies to determine said bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch such that said correction coefficients suitable for input into digital memory of said time-interleaving ADC are obtained.

### Claim 20

A method for operating a time interleaving Analog-to-Digital Converter (ADC), said time interleaving Analog-to-Digital Converter comprising:
a plurality of ADCs;
a timing generator that generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a timing adjustment circuit;
said method comprising, with said timing adjustment circuit:
receiving and adjusting the clock signals before the clock signals are received by the plurality of ADCs; and
adjusting a bandwidth of the plurality of ADCs.

### Claim 21 (depends on 20)

The method of claim 20, further comprising equally spacing said samplings of said input signal in time by operation of said timing adjustment circuit.

### Claim 22 (depends on 20)

The method of claim 20, further comprising adjusting a bandwidth of each of the plurality of ADCs individually.

### Claim 23 (depends on 20)

The method of claim 20, further comprising adjusting a gain of a digital output value of each of the plurality of ADCs.

### Claim 24 (depends on 20)

The method of claim 20, further comprising adjusting an offset of a digital output value of each path through the time-interleaved ADC using an offset coefficient to match an offset of an analog input and an output for each path through the time-interleaved ADC.

### Claim 25 (depends on 24)

The method of claim 24, further comprising adjusting a gain of a digital output value of each path through the time-interleaved ADC using gain coefficient to match gain offset between an analog input and an output for each path through the time-interleaved ADC.

### Claim 26 (depends on 25)

The method of claim 25, further comprising minimizing each of bandwidth mismatch, sample time mismatch, gain mismatch, and offset mismatch using correction coefficients that adjusts the bandwidth, sample time delay, gain, and offset mismatch for each path through one of the ADCs.

### Claim 27 (depends on 26)

The method of claim 26, further comprising determining the bandwidth mismatch, sample time mismatch, gain mismatch and offset mismatch of individual ADC's by employing Fast Fourier Transforms (FFTs) on data collected from operation of the time interleaving Analog-to-Digital Converter at a number of frequencies.

### Claim 28

A time interleaving Analog-to-Digital Converter (ADC), comprising:
a plurality of ADCs;
a timing generator which generates a clock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and
a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate and time adjustment values;
in which the timing adjustment includes time increments smaller than smallest delay created by the clock adjustment circuitry when applied to the ADC.