# US 2014/0152386 A1 · Error amplifier having cascode current source using body biasing

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- Number: US 2014/0152386 A1
- Document ID: US20140152386A1
- Status: Published application
- Kind: A1
- Application number: 13/841,512
- Filed: 2013-03-15
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Industry-Academic Cooperation Foundation, Dankook University; Electronics and Telecommunications Research Institute
- Inventors: Yil Suk YANG; Jongdae Kim; Yong-Seo Koo
- Web page: https://patentgrep.com/patent/US20140152386A1

## CPC

- H03F 3/45192: {Folded cascode stages}
- H03F 2203/45244: the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
- H03F 2203/45508: the CSC comprising a voltage generating circuit as bias circuit for the CSC
- H03F: AMPLIFIERS

## Abstract

Provided is an error amplifier. The error amplifier includes: an amplifying unit receiving first and second input signals and amplifying a voltage difference between the received first and second input signals; a first voltage generating unit generating first and second driving voltages for driving the amplifying unit; a second voltage generating unit generating first and second body voltages to implement a body biasing method; a cascode current source including first to fourth PMOS transistors to provide a bias current to the amplifying unit and the first voltage generating unit; and an output unit outputting a signal of the voltage difference amplified by the amplifying unit, wherein the first and third PMOS transistors receive the first body voltage through a body terminal and the second and fourth PMOS transistors receive the second body voltage through a body terminal.

## Claims

### Claim 1

An error amplifier comprising:
an amplifying unit receiving first and second input signals and amplifying a voltage difference between the received first and second input signals;
a first voltage generating unit generating first and second driving voltages for driving the amplifying unit;
a second voltage generating unit generating first and second body voltages to implement a body biasing method;
a cascode current source including first to fourth PMOS transistors to provide a bias current to the amplifying unit and the first voltage generating unit; and
an output unit outputting a signal of the voltage difference amplified by the amplifying unit,
wherein the first and third PMOS transistors receive the first body voltage through a body terminal and the second and fourth PMOS transistors receive the second body voltage through a body terminal.

### Claim 2 (depends on 1)

The error amplifying unit of claim 1, wherein
the second voltage generating unit comprises first and second NMOS transistors;
body terminals of the first and third PMOS transistors are connected to a gate terminal of the first NMOS transistor to receive the first body voltage; and
body terminals of the second and fourth PMOS transistors are connected to a gate terminal of the second NMOS transistor to receive the second body voltage.

### Claim 3 (depends on 2)

The error amplifier of claim 2, wherein the cascode current source comprises a plurality of first PMOS transistors where current is copied in response to the first PMOS transistor and a plurality of second PMOS transistors where current is copied in response to the second PMOS transistor.

### Claim 4 (depends on 3)

The error amplifier of claim 3, wherein
each of body terminals of the plurality of first PMOS transistors is connected to the gate terminal of the first NMOS transistor to receive the first body voltage; and
each of body terminals of the plurality of second PMOS transistors is connected to the gate terminal of the second NMOS transistor to receive the second body voltage.

### Claim 5 (depends on 2)

The error amplifier of claim 2, further comprising a reference current source determining the size of the bias current from the cascode current source.

### Claim 6 (depends on 2)

The error amplifier of claim 2, further comprising a resistor generating a driving voltage in the first and second PMOS transistors.

### Claim 7 (depends on 2)

The error amplifier of claim 2, wherein the amplifying unit comprises an input unit and an output unit,
wherein
the input unit comprises a first MOS transistor receiving the first input signal and a second MOS transistor receiving the second input signal; and
the output unit comprises third and fourth MOS transistors amplifying a voltage difference outputted through the first and second MOS transistors.

### Claim 8 (depends on 7)

The error amplifier of claim 7, wherein the output unit comprises a fifth MOS transistor providing a driving current to the third MOS transistor and a sixth MOS transistor providing a driving current to the fourth transistor.

### Claim 9 (depends on 8)

The error amplifier of claim 8, wherein
gate terminals of the third and fourth MOS transistors are connected to each other and receive the first driving voltage from the first voltage generating unit; and
gate terminals of the fifth and sixth MOS transistors are connected to each other and receive the second driving voltage from the first voltage generating unit.

### Claim 10 (depends on 9)

The error amplifier of claim 9, wherein the first voltage generating unit operates by receiving the bias current from the first current source.

### Claim 11 (depends on 10)

The error amplifier of claim 10, wherein according to a voltage difference between the first and second signals outputted from the third and fourth MOS transistors, the output unit outputs the voltage difference through an output terminal.

### Claim 12 (depends on 11)

The error amplifier of claim 11, wherein gate terminals of the seventh and eighth MOS transistors are connected to each other and have a current mirror type structure.