# US 2014/0152383 A1 · Integrated circuits and systems and methods for producing the same

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- Number: US 2014/0152383 A1
- Document ID: US20140152383A1
- Status: Published application
- Kind: A1
- Application number: 13/690,407
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Intel Corporation
- Inventors: DMITRI E. NIKONOV; ROBERT L. SANKMAN; RASEONG KIM; JIN PAN
- Web page: https://patentgrep.com/patent/US20140152383A1

## CPC

- B32B 27/06: as the main or only constituent of a layer, {which is} next to another layer of {the same or of} a {different material (next to a layer of a particular substance B32B9/045; next to a bituminous or tarry layer B32B11/046; next to a water setting substance layer B32B13/12; next to a metal layer B32B15/08; next to a glass layer B32B17/10; next to a layer formed of natural mineral fibres or particles B32B19/045; next to a wood layer B32B21/08; next to a cellulosic plastic layer B32B23/08; next to a natural or synthetic rubber layer B32B25/08)}
- B33Y 70/00: Materials specially adapted for additive manufacturing
- B33Y 80/00: Products made by additive manufacturing
- H05K 1/00: Printed circuits
- H05K 3/4644: {by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10K 19/201: {Integrated devices having a three-dimensional layout, e.g. 3D ICs}
- H10K 71/13: using printing techniques, e.g. ink-jet printing or screen printing
- B32B 2457/00: Electrical equipment
- B33Y 50/02: for controlling or regulating additive manufacturing processes
- B32B: LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B33Y: ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Three dimensional integrated circuits including semiconductive organic materials are described. In some embodiments, the three dimensional integrated circuits include one or more electronic components that include a semiconductive region formed of one or more semiconductive organic materials. The electronic components of the three dimensional integrated circuits may also include insulating regions formed from organic insulating materials, and conductive regions form from conductive materials. The three dimensional integrated circuits may be formed by an additive manufacturing process such as three dimensional printing. Apparatus and methods for producing and testing three dimensional integrated circuits are also described.

## Claims

### Claim 1

A method for producing integrated circuits, comprising:
processing with a host processor of a computing device a digital model of said integrated circuit into a plurality of layers; and
iteratively forming said plurality of layers on a support with an additive manufacturing apparatus so as to produce an operable physical copy of said model; wherein:
said integrated circuit includes at least one electronic component comprising at least one semiconductive region; and
said at least one semiconductive region is reproduced in said physical copy with at least one semiconductive organic material.

### Claim 2 (depends on 1)

The method of claim 1, wherein said additive manufacturing apparatus includes at least one print head, said at least one print head comprising at least one deposition mechanism and at least one curing mechanism.

### Claim 3 (depends on 2)

The method of claim 2, wherein said additive manufacturing apparatus is configured to iteratively deposit said plurality of layers by at least one of fused deposition modeling, stereolithography, and granular materials binding.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
said digital model of said integrated circuit comprises a plurality of electronic components comprising at least one semiconductive region; and
said at least one semiconductive region is reproduced in said physical copy of said digital model with said at least one semiconductive organic material.

### Claim 5 (depends on 4)

The method of claim 4, wherein:
said plurality of electronic components further comprise at least one electrically insulating region and at least one electrically conductive region; and
said at least one electrically insulating region and said at least one electrically conductive region are reproduced in said physical copy of said digital model with at least one organic insulating material and at least one conductive material, respectively.

### Claim 6 (depends on 4)

The method of claim 4, wherein said at least one semiconductive organic material is selected from the group consisting of pentacene, rubrene, hexadecafluorocopperphthalocyanine, perylene-tetracarboxylic dianhydride, napthalene-tetracarboxylic dianhydride, copper phthalocyanine, α-sexithiophene, 6,13-Bis(tri-isopropylsilylethynyl) pentacene, N, N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide, 4,4′-bis[N-(1-Napthyl)-N-phenyl-amino]-biphenyl, α-napthylphenylbiphenyl diamine, p-doped polyacetylene, n-doped polyacetylene, and combinations thereof.

### Claim 7 (depends on 5)

The method of claim 5, wherein said at least one organic insulating material is polyethylene.

### Claim 8 (depends on 5)

The method of claim 5, wherein said at least one conductive material is selected from the group consisting of copper, aluminum, gold, rubrene, and combinations thereof.

### Claim 9 (depends on 1)

The method of claim 1, wherein when a layer of said plurality of layers comprises multiple materials, the method further comprises processing said layer of said plurality of layers with said host processor into a plurality of voxels, wherein each of said plurality of voxels define a region of one of said multiple materials.

### Claim 10 (depends on 1)

The method of claim 1, wherein said integrated circuit comprises multiple layers of electronic components.

### Claim 11 (depends on 1)

The method of claim 1, wherein said integrated circuit is a three dimensional integrated circuit.

### Claim 12

A three dimensional printing apparatus, comprising:
a controller;
a print head; and
a materials store;
wherein:
said controller is configured to process a digital model of an integrated circuit into a plurality of layers with a host processor;
said integrated circuit includes at least one electronic component comprising at least one semiconductive region; and
said print head is configured to produce an operable physical copy of said integrated circuit by iteratively depositing on a support each of said plurality of layers using one or more materials contained in said materials store.

### Claim 13 (depends on 12)

The three dimensional printing apparatus of claim 12, wherein said print head comprises at least one deposition mechanism and at least one curing mechanism, wherein said deposition mechanism is configured to produce layers of uncured material from said materials store on said support, and said curing mechanism is configured to cure said layers of uncured material.

### Claim 14 (depends on 13)

The three dimensional printing apparatus of claim 13, wherein said deposition mechanism produces said layers of uncured material by at least one of:
extruding a molten extrudate of a material in said materials store on said support;
depositing particles of a material in said materials store on said support; and
forming a layer of photopolymerizable material from said materials store on said support.

### Claim 15 (depends on 14)

The three dimensional printing apparatus of claim 14, wherein said curing mechanism cures said layers of uncured material by applying at least one of light and heat to said layers.

### Claim 16 (depends on 12)

The three dimensional printing apparatus of claim 12, wherein said print head comprises a plurality of nozzles.

### Claim 17 (depends on 12)

The three dimensional printing apparatus of claim 12, wherein said materials store contains at least one semiconductive organic material, and said print head is configured to physically reproduce said at least one semiconductive region with said at least one semiconductive organic material.

### Claim 18 (depends on 17)

The three dimensional printing apparatus of claim 17, wherein said digital model further comprises an electrically insulating region and an electrically conductive region, said materials store contains at least one organic insulating material and at least one conductive material, and said print head is configured to physically reproduce said electrically insulating region and electrically conductive region with said at least one organic insulating material and at least one conductive material, respectively.

### Claim 19 (depends on 12)

The three dimensional printing apparatus of claim 12, wherein said integrated circuit comprises multiple layers of electronic components.

### Claim 20 (depends on 12)

The three dimensional printing apparatus of claim 12, wherein said integrated circuit is a three dimensional integrated circuit.

### Claim 21

A three dimensional integrated circuit comprising a plurality of electronic components, wherein at least one of said plurality electronic components comprises a semiconductive region formed from at least one semiconductive organic material.

### Claim 22 (depends on 21)

The three dimensional integrated circuit of claim 21, wherein said semiconductive organic material is selected from the group consisting of pentacene, rubrene, hexadecafluorocopperphthalocyanine, perylene-tetracarboxylic dianhydride, napthalene-tetracarboxylic dianhydride, copper phthalocyanine, α-sexithiophene, 6,13-Bis(tri-isopropylsilylethynyl) pentacene, N, N′-ditridecylperylene-3,4,9,10-tetracarboxylic diimide, 4,4′-bis[N-(1-napthyl)-n-phenyl-amino]-biphenyl, α-napthylphenylbiphenyl diamine, p-doped polyacetylene, n-doped polyacetylene, and combinations thereof.

### Claim 23 (depends on 21)

The three dimensional integrated circuit of claim 21, wherein said at least one of said plurality of electronic components further comprises an electrically insulating region formed from at least one organic insulating material.

### Claim 24 (depends on 23)

The three dimensional integrated circuit of claim 23, wherein said organic insulating material is polyethylene.

### Claim 25 (depends on 21)

The three dimensional integrated circuit of claim 21, wherein said at least one of said plurality of electronic components further comprises a conductive region formed from a conductive material.

### Claim 26 (depends on 25)

The three dimensional integrated circuit of claim 25, wherein said conductive material is selected from copper, gold, aluminum, rubrene, and combinations thereof.

### Claim 27 (depends on 25)

The three dimensional integrated circuit of claim 25, wherein said at least one of said plurality of electronic components is an active electronic component or a passive electronic component.

### Claim 28 (depends on 25)

The three dimensional integrated circuit of claim 25, wherein said at least one of said plurality of electronic components is a transistor, a diode, or an optoelectronic device.

### Claim 29 (depends on 21)

The three dimensional integrated circuit of claim 21, wherein said semiconductive region comprises a gate, a channel, a source, a drain, a base, an emitter, a collector, or a combination thereof.

### Claim 30

A method for testing an integrated circuit, comprising: converting with a host processor of a computing device a first digital model of said integrated circuit to a second digital model of said integrated circuit, wherein:
said integrated circuit includes a plurality of electronic components that comprise one or more semiconductive regions;
said first model designates the use of one or more inorganic semiconductive materials for said semiconductive regions; and
said second digital model designates the use of one or more semiconductive organic materials for said semiconductive regions.

### Claim 31 (depends on 30)

The method of claim 30, wherein:
said plurality of electronic components further comprise one or more electrically insulating regions;
said first digital model designates the use of one or more inorganic insulating materials for said electrically insulating regions; and
said second digital model designates the use of one or more organic insulating materials for said electrically insulating regions.

### Claim 32 (depends on 30)

The method of claim 30, further comprising producing an operable physical copy of said second digital model using an additive manufacturing apparatus.

### Claim 33 (depends on 30)

The method of claim 30, wherein said producing an operable physical copy comprises:
processing said second digital model of said three dimensional integrated circuit with said host processor into a plurality of layers; and
iteratively forming said plurality of layers on a support with an additive manufacturing apparatus so as to produce a physical copy of said second digital model;
wherein said semiconductive regions in said second digital model are reproduced in said physical copy using said one or more semiconductive organic materials.

### Claim 34 (depends on 33)

The method of claim 33, wherein:
said first digital model designates the use of one or more inorganic insulating materials for said electrically insulating regions;
said second model designates the use of one or more organic insulating materials for said electrically insulating regions; and
said electrically insulating regions are reproduced in said physical copy using said one or more organic insulating materials.

### Claim 35 (depends on 32)

The method of claim 32, further comprising testing at least one parameter of said operable physical copy.

### Claim 36 (depends on 35)

The method of claim 35, further comprising modifying at least one of said first and second models based on said testing, thereby producing a modified first model, a modified second model, or a combination thereof.

### Claim 37 (depends on 36)

The method of claim 36, further comprising producing a modified physical copy of said integrated circuit based on said modified first model, modified second model, or a combination thereof.

### Claim 38 (depends on 30)

The method of claim 30, wherein said integrated circuit comprises multiple layers of electronic components.

### Claim 39 (depends on 30)

The method of claim 30, wherein said integrated circuit is a three dimensional integrated circuit.

### Claim 40

A computer readable medium having three dimensional model conversion (3DMC) instructions stored thereon, wherein said 3DMC instructions when executed by a processor cause said processor to perform the following operations comprising:
converting a first digital model of an integrated circuit to a second digital model of said integrated circuit, wherein:
said integrated circuit includes a plurality of electronic components that comprise one or more semiconductive regions;
said first model designates the use of one or more semiconductive inorganic materials for said semiconductive regions; and
said second digital model designates the use of one or more semiconductive organic materials for said semiconductive regions.

### Claim 41 (depends on 40)

The computer readable medium of claim 40, wherein said 3DMC instructions when executed further cause said processor, during said converting, to:
associate the inorganic semiconductive materials designated by said first digital model with one or more organic semiconductive materials; and
designate said organic semiconductive materials for use in corresponding semiconductive regions in said second model.

### Claim 42 (depends on 40)

The computer readable medium of claim 40, wherein said 3DMC instructions when executed further cause said processor to:
process said second digital model into a plurality of layers; and
output a signal to an additive manufacturing apparatus, wherein said signal is configured to cause said additive manufacturing apparatus to produce an operable physical copy of said second digital model.

### Claim 43 (depends on 42)

The computer readable medium of claim 42, wherein said signal is configured to cause said additive manufacturing apparatus to iteratively form said plurality of layers on a support, such that said one or more semiconductive regions in said second digital model are reproduced in said physical copy using said one or more semiconductive organic materials.

### Claim 44 (depends on 41)

The computer readable medium of claim 41, wherein said 3DMC instructions when executed further cause said processor, during said converting, to:
associate inorganic insulating materials designated by said first digital model for use in one or more electrically insulating regions of said three dimensional integrated circuit with one or more organic insulating materials; and
designate said organic insulating materials for use in corresponding electrically insulating regions of said second model.

### Claim 45 (depends on 42)

The computer readable medium of claim 42, wherein said signal causes said additive manufacturing system to produce said one or more electrically insulating regions in said physical copy with said one or more organic insulating materials.