# US 2014/0152382 A1 · Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (ic) chip including the circuit and method of switching voltage on chip

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- Number: US 2014/0152382 A1
- Document ID: US20140152382A1
- Status: Published application
- Kind: A1
- Application number: 13/727,580
- Filed: 2012-12-26
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: International Business Machines Corporation
- Inventors: Leland Chang; Robert Montoye; Jae-sun Seo
- Web page: https://patentgrep.com/patent/US20140152382A1

## CPC

- G11C 5/00: Details of stores covered by group G11C11/00
- G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)}
- G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits}
- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H02M 3/072: {adapted to generate an output voltage whose value is lower than the input voltage}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes.

## Claims

### Claim 1

A method of configuring on-chip supply voltage being supplied to one or more chip circuits, said method comprising:
selecting a first voltage supply mode;
floating one side of a first capacitor in a pair of series connected capacitors, the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair;
alternately switching opposite sides of said second capacitor to a voltage supply output (Vout), one side of said second capacitor being alternately switched between a first supply voltage and said voltage supply output, the other side of said second capacitor being alternately switched between a second supply voltage and said voltage supply output, said voltage supply output supplying a first output voltage;
selecting a second voltage supply mode;
alternately floating and coupling said one side of said first capacitor to said first supply voltage and simultaneously switching the other side of said second capacitor to said voltage supply output when said one side is floating, said first side of said second capacitor being alternately switched in and out to said voltage supply output, the other side of said second capacitor being alternately switched between said second supply voltage and said voltage supply output, said voltage supply output supplying a second output voltage; and
waiting to reselect said first voltage supply mode.

### Claim 2 (depends on 1)

A method of configuring on-chip supply voltage as in claim 1, wherein in said first voltage supply mode alternately switching said opposite sides comprises:
floating one side of a first capacitor in a pair of series connected capacitors, the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair;
asserting a first clock;
coupling said first side of said second capacitor to said first supply voltage responsive to said first clock;
coupling the other side of said second capacitor to said supply voltage output responsive to said first clock;
asserting a second clock, said first clock and said second clock not overlapping;
coupling said first side of said second capacitor to said supply voltage output responsive to said second clock;
coupling the other side of said second capacitor to said second supply voltage responsive to said second clock; and
returning to asserting said first clock.

### Claim 3 (depends on 2)

A method of configuring on-chip supply voltage as in claim 2, wherein in said second voltage supply mode alternately floating and coupling said one side and alternately switching said opposite sides comprises:
asserting said first clock;
coupling said one side of said first capacitor to said first supply voltage responsive to said first clock;
coupling said other side of said second capacitor to said voltage supply output responsive to said first clock;
asserting a second clock, said one side of said second capacitor being floated;
coupling said other side of a said first capacitor to said voltage supply output responsive to said second clock;
coupling said other side of said second capacitor to said second supply voltage responsive to said second clock; and
returning to asserting said first clock.

### Claim 4 (depends on 3)

A method of configuring on-chip supply voltage as in claim 3, wherein said first capacitor is connected between a pair of FETs and floating said one side of said first capacitor comprises gating both FETs off.

### Claim 5 (depends on 4)

A method of configuring on-chip supply voltage as in claim 4, wherein floating said one side of said first capacitor further comprises gating on an FET shorting the opposite ends of both off FETs.

### Claim 6 (depends on 5)

A method of configuring on-chip supply voltage as in claim 5, wherein said chip is a CMOS chip, said pair of FETs is a PFET and an NFET in a FET totem including alternate PFETs and NFETs;
said other side of said first capacitor and said first side of a second capacitor of the series connected capacitor pair being connected between a second PN FET pair; and
said other side of said second capacitor being connected between a second PN FET pair.

### Claim 7 (depends on 6)

A method of configuring on-chip supply voltage as in claim 6, wherein asserting said first clock turns on totem PFETs and asserting said second clock turns on totem NFETs, the first PN FET pair being gated by said first clock and said second clock when said second mode is selected.

### Claim 8 (depends on 7)

A method of configuring on-chip supply voltage as in claim 7, wherein said second supply voltage is a supply return for said first supply voltage (Vin).

### Claim 9

A method of configuring on-chip supply voltage being supplied to one or more chip circuits, said method comprising:
selecting a first voltage supply mode;
floating one side of a first capacitor in a pair of series connected capacitors, the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair; and while said first voltage supply mode is selected,
asserting a first clock;
coupling said first side of said second capacitor to a first voltage supply line responsive to said first clock;
coupling the other side of said second capacitor to an on-chip supply voltage output (Vout)responsive to said first clock;
asserting a second clock, said first clock and said second clock not overlapping;
coupling said first side of said second capacitor to said on-chip supply voltage output responsive to said second clock;
coupling the other side of said second capacitor to a second voltage supply line responsive to said second clock; and
returning to assert said first clock.

### Claim 10 (depends on 9)

A method of configuring on-chip supply voltage as in claim 9, said method further comprising:
selecting a second voltage supply mode; and while said second voltage supply mode is selected,
asserting said first clock;
coupling said one side of said first capacitor to said first voltage supply line responsive to said first clock;
coupling said other side of said second capacitor to said on-chip supply voltage output responsive to said first clock;
asserting a second clock;
coupling said one side of a said first capacitor to said on-chip supply voltage output responsive to said second clock;
coupling said other side of said second capacitor to said second voltage supply line responsive to said second clock; and
returning to assert said first clock.

### Claim 11 (depends on 10)

A method of configuring on-chip supply voltage as in claim 10, wherein said first voltage supply mode is a 2:1 configuration mode, said second voltage supply mode is a 3:1 configuration mode and upon a next selection of said 2:1 mode, said method further comprising returning to float said one side of said first capacitor.

### Claim 12 (depends on 11)

A method of configuring on-chip supply voltage as in claim 11, wherein said first capacitor is connected between a pair of FETs and floating said one side of said first capacitor comprises gating both FETs off.

### Claim 13 (depends on 12)

A method of configuring on-chip supply voltage as in claim 12, wherein one of said first voltage supply line and said second voltage supply line is a supply return line and the other is a chip supply (Vin), floating said one side of said first capacitor further comprises gating on an FET shorting the opposite ends of both off FETs, and Vin:Vout is selectable as 2:1 or 3:1.

### Claim 14 (depends on 13)

A method of configuring on-chip supply voltage as in claim 13, wherein said chip is a CMOS chip, said pair of FETs is a PFET and an NFET in a FET totem including alternate PFETs and NFETs;
said other side of said first capacitor and said first side of a second capacitor of the series connected capacitor pair being connected between a second PN FET pair; and
said other side of said second capacitor being connected between a second PN FET pair.

### Claim 15 (depends on 14)

A method of configuring on-chip supply voltage as in claim 14, wherein asserting said first clock turns on totem PFETs and asserting said second clock turns on totem NFETs, the first PN FET pair being gated by said first clock and said second clock when said second mode is selected.

### Claim 16 (depends on 15)

A method of configuring on-chip supply voltage as in claim 15, wherein said second supply voltage line is said supply return for said first supply voltage line (Vin).

### Claim 17

A method of configuring on-chip supply voltage being supplied to one or more CMOS chip circuits, said method comprising:
selecting a first voltage supply mode;
floating one side of a first capacitor in a pair of series connected capacitors connected to a field effect transistor (FET) totem connected between a first supply (V1) and a second supply (V2), the other side of said first capacitor being connected to a first side of a second capacitor of the series connected pair, said one side being connected between a first PFET and NFET (PN FET) totem pair, said other side and said first side being connected between a second PN FET totem pair and the opposite side of said second capacitor being connected between a third PN FET totem pair;
alternately turning PFETs off and on and NFETs on and off in the second and third PN FET totem pair, said second and third PN FET totem pairs alternately switching opposite sides of said second capacitor to a voltage supply output (Vout);
selecting a second voltage supply mode;
alternately turning PFETs off and on and NFETs on and off in the first, second and third PN FET totem pairs, said first PN FET totem pair alternately floating and coupling said one side of said first capacitor to V1, and said second and third PN FET totem pairs simultaneously alternately switching said other side of said second capacitor to Vout when said one side is floating, said second and third PN FET totem pairs alternately switching opposite sides of said second capacitor to Vout; and
waiting to reselect said first voltage supply mode.

### Claim 18 (depends on 17)

A method of configuring on-chip supply voltage as in claim 17, wherein in said first voltage supply mode alternately switching said opposite sides comprises:
in a first half cycle PFETs in both said the second and third PN FET totem pair being switched on, said PFET in said second PN FET totem pair switching said first side of said second capacitor to V1, and said PFET in said third PN FET totem pair switching said opposite side of said second capacitor to Vout, the corresponding NFETs in both pair being off; and
in a second half cycle by switching PFETs off and NFETs on, on NFETs switching said first side of said second capacitor to Vout and said other side of said second capacitor to V2.

### Claim 19 (depends on 18)

A method of configuring on-chip supply voltage as in claim 18, wherein floating one side in said first voltage supply mode comprises:
shorting said first PN FET pair; and
holding off both the PFET and NFET in said first PN FET pair, said first side being connected between said PFET and NFET.

### Claim 20 (depends on 19)

A method of configuring on-chip supply voltage as in claim 19, wherein V1 is Vin, V2 is ground and shorting said first PN FET pair comprises turning on a shunting PFET in parallel with said first PN FET pair.

### Claim 21 (depends on 20)

A method of configuring on-chip supply voltage as in claim 20, wherein alternately switching said opposite sides in said first voltage supply mode comprises:
asserting a PFET clock low, an NFET clock being low while said PFET clock is asserted, said PFET in said second PN FET pair coupling said first side of said second capacitor to one side of said shunt PFET, said PFET in said third PN FET pair coupling said other side of said second capacitor to said Vout;
driving said PFET clock high;
asserting said NFET clock high, said NFET in said second PN FET pair coupling said first side of said second capacitor to Vout, said NFET in said third PN FET pair coupling the other side of said second capacitor to said supply return;
driving said NFET clock low; and
returning to asserting said PFET clock low.

### Claim 22 (depends on 21)

A method of configuring on-chip supply voltage as in claim 21, wherein alternately floating and coupling said one side of said first capacitor in said second voltage supply mode comprises:
turning said shunting PFET off; and
passing said PFET clock through a PFET clock gate to the gate of said PFET in said first PN FET pair and said NFET through an NFET clock gate to the gate of said NFET in said first PN FET pair.

### Claim 23 (depends on 19)

A method of configuring on-chip supply voltage as in claim 19, wherein V1 is ground, V2 is Vin, shorting said first PN FET pair comprises turning on a shunting NPFET in parallel with said first PN FET pair, and Vin:Vout is selectable as 2:1 in said first voltage supply mode or 3:1 in said second voltage supply mode.

### Claim 24

A method of configuring on-chip supply voltage being supplied to one or more CMOS chip circuits, said method comprising:
asserting a configuration select in a first state, said first state selecting a first voltage supply mode;
turning a shunting field effect transistor (FET) on, said shunting FET shorting a first PFET and NFET pair (PN FET pair) in a FET totem connected between a first supply voltage (V1) and a second supply voltage (V2), one side of a first capacitor in a pair of series connected capacitors connected between the PFET and NFET in said first PN FET pair;
blocking a PFET clock and an NFET clock to said first PN FET pair, both the PFET and NFET in said first PN FET pair being held off, said one side of said first capacitor floating;
switching on PFETs in said the second and third PN FET totem pair in a first half cycle, said PFET in said second PN FET totem pair switching said first side of said second capacitor to V1, and said PFET in said third PN FET totem pair switching the opposite side of said second capacitor to Vout, the corresponding NFETs in both pair being off;
switching said PFETs off in a second half cycle and NFETs on, on NFETs switching said first side of said second capacitor to Vout and said other side of said second capacitor to V2;
returning to switching on PFETs until said configuration select is asserted in a second state, and when asserted in said second state a second voltage supply mode has been selected; and then
turning off said shunting FET;
passing said PFET clock and said NFET clock to said first PN FET pair, both the PFET and NFET in said first PN FET pair being gated on by a respective clock;
switching on PFETs in the first, second and third PN FET totem pairs in a first half cycle, said PFET in said first PN FET totem pair switching said one side of said first capacitor to V1, and said PFET in said third PN FET totem pair switching the opposite side of said second capacitor to Vout, the corresponding NFETs in said first, second and third PN FET totem pairs being off;
switching said PFETs off in a second half cycle and NFETs on, on NFETs switching said first side of said second capacitor to Vout and said other side of said second capacitor to V1; and
returning to switching on PFETs in all three PN FET totem pairs until said first voltage supply mode is reselected.

### Claim 25 (depends on 24)

A method of configuring on-chip supply voltage as in claim 24, wherein V1 is Vin, V1 is ground, and Vin:Vout is selectable as 2:1 in said first voltage supply mode or 3:1 in said second voltage supply mode.