# US 2014/0152381 A1 · Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (ic) chip including the circuit and method of switching voltage on chip > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152381 A1 - Document ID: US20140152381A1 - Status: Published application - Kind: A1 - Application number: 13/690,985 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Leland Chang; Robert Montoye; Jae-sun Seo - Web page: https://patentgrep.com/patent/US20140152381A1 ## CPC - G11C 5/00: Details of stores covered by group G11C11/00 - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H02M 3/072: {adapted to generate an output voltage whose value is lower than the input voltage} - G11C: STATIC STORES (semiconductor memory devices H10B) - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract A configurable-voltage converter circuit that may be CMOS and an integrated circuit chip including the converter circuit and method of operating the IC chip and circuit. A transistor totem, e.g., of 6 or more field effect transistors, PFETs and NFETs, connected (PNPNPN) between a first supply (Vin) line and a supply return line. A first switching capacitor is connected between first and second pairs of totem PN FETs pair of transistors. A second switching capacitor is connected between the second and a third pair of totem FETs. A configuration control selectively switches both third FETs off to float the connected end of the second capacitor, thereby switching voltage converter modes. ## Claims ### Claim 1 A configurable-voltage converter circuit comprising: a transistor totem connected between a first supply (Vin) line and a second supply line; a first switching capacitor connected at one end between a first pair of totem transistors and at the opposite end between a second pair of totem transistors; a second switching capacitor connected at one end between said second pair of totem transistors and at said opposite end between a third pair of totem transistors; a configuration control selectively switching both of said third pair of totem transistors off, said opposite end of said second switching capacitor being isolated when said third pair is switched off; and a supply output between one transistor in said first pair of totem transistors and a transistor in said second pair of totem transistors, voltage on said supply output being selected by said configuration control. ### Claim 2 (depends on 1) A configurable-voltage converter circuit as in claim 1, wherein said transistor totem is a plurality of first conduction type transistors alternating with a plurality of second conduction type transistors connected between said first supply (Vin) line and said second supply line, each pair of totem transistors being one of said first conduction type transistors and one of said second conduction type transistors. ### Claim 3 (depends on 2) A configurable-voltage converter circuit as in claim 2, wherein said configuration control comprises a shunt transistor in parallel with said third pair of said totem transistors, and a pair of clock select circuits, said shunt transistor and said pair of clock select circuits being gated by a configuration select signal. ### Claim 4 (depends on 3) A configurable-voltage converter circuit as in claim 3 receiving a pair of non-overlapping clock phases including a first phase gating first conduction type transistors and a second phase gating second conduction type transistors, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal. ### Claim 5 (depends on 4) A configurable-voltage converter circuit as in claim 4, wherein said second supply line is a supply return line, said configurable-voltage converter circuit is a CMOS converter, said first conduction type is N-type and said second conduction type is P-type. ### Claim 6 (depends on 5) A configurable-voltage converter circuit as in claim 5, wherein said pair of clock select circuits comprise a PFET clock select circuit and an NFET clock select circuit passing respective clock phases responsive to said configuration signal being at a first level and blocking said respective clock phases responsive to said configuration signal being at a second level. ### Claim 7 (depends on 6) A configurable-voltage converter circuit as in claim 6, wherein said supply output is at a first supply level when said configuration signal is at said first level, and said supply output is at a second supply level when said configuration signal is at said second level. ### Claim 8 (depends on 7) A configurable-voltage converter circuit as in claim 7, wherein: said PFET clock select circuit comprises a pair of NAND gates, the first NAND gate NANDing a PFET clock phase with said configuration signal and said second NAND gate NANDing the output of said first NAND gate with said configuration signal; said NFET clock select circuit comprises a NAND gate NANDing an NFET clock phase with said configuration signal, an inverter and an NAND-NOR NANDing the output of said first NAND gate with said configuration signal and NORing the result with an inverted said configuration signal; and said configuration signal being high configures said configurable-voltage converter circuit in three to one (3:1) mode and said configuration signal being low configures said configurable-voltage converter circuit in three to one (2:1) mode. ### Claim 9 (depends on 5) A configurable-voltage converter circuit as in claim 5, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (Vin) line. ### Claim 10 (depends on 5) A configurable-voltage converter circuit as in claim 5, wherein the NFET of the third PN FET pair is connected at one conduction terminal to said first supply return line. ### Claim 11 A CMOS configurable-voltage converter circuit comprising: a field effect transistor (FET) totem of alternate P-type FETs (PFETs) and N-type FETs (NFETs) connected between a first supply (Vin) line and a second supply line; a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks; a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs; a configuration control comprising a shunt transistor in parallel with said third pair of said totem transistors gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off and said shunt transistor on, said opposite end of said second switching capacitor being isolated when the third PN FET pair is switched off; and a supply output between one FET in said first PN pair of totem FETs and an opposite type FET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control. ### Claim 12 (depends on 11) A CMOS configurable-voltage converter circuit as in claim 11, wherein said configuration control further comprises a pair of clock select circuits, each being one of a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks, and each being gated by said configuration select signal. ### Claim 13 (depends on 12) A CMOS configurable-voltage converter circuit as in claim 12, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal. ### Claim 14 (depends on 13) A CMOS configurable-voltage converter circuit as in claim 13, wherein said PFET clock select circuit and said NFET clock select circuit pass respective clock phases responsive to said configuration signal being at a first level and block said respective clock phases responsive to said configuration signal being at a second level, said first level selecting a three to one (3:1) configuration and said second level selecting a two to one (2:1) configuration. ### Claim 15 (depends on 14) A configurable-voltage converter circuit as in claim 14, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (Vin) line. ### Claim 16 (depends on 14) A configurable-voltage converter circuit as in claim 14, wherein the NFET of the third PN FET pair is connected at one conduction terminal to said second supply line. ### Claim 17 An CMOS integrated circuit (IC) chip comprising: a supply voltage line to an IC chip; a supply return line to said IC chip; a plurality of circuits on said IC chip, at least one circuit operating at a plurality of voltages lower than said supply voltage; a configurable-voltage converter circuit comprising: a field effect transistor (FET) totem of alternate P-type FETs (PFETs) and N-type FETs (NFETs) connected between a first supply line and a second supply line, said first supply line being coupled to Vin and said second supply line being coupled to said supply return line, a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks, a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs, a configuration control comprising a shunt transistor in parallel with said third pair of said totem transistors gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off and said shunt transistor on, said opposite end of said second switching capacitor being isolated when the third PN FET pair is switched off, and a supply output (Vout) between one FET in said first PN pair of totem FETs and an opposite type FET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control. ### Claim 18 (depends on 17) A CMOS IC chip as in claim 17, wherein said configuration control further comprises a pair of clock select circuits, each being one of a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks, and each gated by a configuration select signal. ### Claim 19 (depends on 18) A CMOS IC chip as in claim 18, wherein each phase is an input to one of said pair of clock select circuits, each clock circuit passing a respective phase responsive to said configuration select signal. ### Claim 20 (depends on 19) A CMOS IC chip as in claim 19, wherein said PFET clock select circuit and said NFET clock select circuit pass respective clock phases responsive to said configuration signal being at a first level and block said respective clock phases responsive to said configuration signal being at a second level, said first level selecting a three to one (3:1) configuration and said second level selecting a two to one (2:1) configuration. ### Claim 21 (depends on 19) A CMOS IC chip as in claim 19, wherein the PFET of the third PN FET pair is connected at one conduction terminal to said first supply (Vin) line. ### Claim 22 (depends on 19) A CMOS IC chip as in claim 19, wherein the NFET of the third PN FET pair is connected at one conduction terminal to a supply return line. ### Claim 23 An CMOS integrated circuit (IC) chip comprising: a supply voltage line to an IC chip; a supply return line to said IC chip; a plurality of circuits on said IC chip, at least one circuit operating at a pair of voltages lower than said supply voltage; a configurable-voltage converter circuit, configurable between three to one (3:1) and two to one (2:1) voltage conversion, comprising: a field effect transistor (FET) totem of three P-type FETs (PFETs) and three N-type FETs (NFETs) serially connected alternating P and N FETs between a first supply line and said a second supply line, a first switching capacitor connected at one end between a first PN pair of totem FETs and at the opposite end between a second PN pair of totem FETs, the NFET of said first PN pair being further connected to said second supply line, the first PN pair of FETs and the second PN pair of FETs being gated by a pair of non-overlapping clocks, a second switching capacitor connected at one end between said PN second pair of totem FETs and at said opposite end between a third PN pair of totem FETs, the PFET of said third PN pair being further connected to first supply line, a configuration control gated by a configuration select signal and selectively passing said pair of non-overlapping clocks or switching both of said third PN pair of totem FETs off, said configuration select signal selecting between 3:1 and 2:1, said configuration select signal turning off said third PN FET pair in 2:1 mode, said third PN FET pair being gated by said pair of non-overlapping clocks in 3:1 mode, and a supply output between the PFET in said first PN pair of totem FETs and the NFET in said second PN pair of totem FETs, voltage on said supply output being selected by said configuration control. ### Claim 24 (depends on 23) A CMOS IC chip as in claim 23, wherein said configuration control comprises a shunt PFET in parallel with said third PN pair of said totem FETs, a PFET clock select circuit and an NFET clock select circuit, each receiving one phase of said pair of non-overlapping clocks and each gated by said configuration select signal, said configuration select signal gating said shunt PFET. ### Claim 25 (depends on 24) A CMOS IC chip as in claim 24, wherein said first supply (Vin) line is coupled to said supply voltage line and said second supply line is coupled to said supply return line. ### Claim 26 (depends on 1) A configurable-voltage converter circuit as in claim 1, wherein said configuration control comprises a shunt transistor in parallel with said third pair of said totem transistors, said shunt transistor being gated by a configuration select signal.