# US 2014/0152380 A1 · Semiconductor device that can cancel noise in bias line to which bias current flows > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152380 A1 - Document ID: US20140152380A1 - Status: Published application - Kind: A1 - Application number: 14/174,670 - Filed: 2014-02-06 - Published: 2014-06-05 - Earliest claimed: 2011-02-22 - Assignees: Elpida Memory, Inc. - Applicants: Elpida Memory, Inc. - Inventors: Hideyuki YOKOU; Isao NAKAMURA; Manabu ISHIMATSU - Web page: https://patentgrep.com/patent/US20140152380A1 ## CPC - H02M 7/003: {Constructional details, e.g. physical layout, assembly, wiring or busbar connections} - H03K 19/00361: {in field effect transistor circuits} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Disclosed herein is a device that includes a bias line to which a bias current flows, a switch circuit controlling an amount of the bias current based on a control signal, a control line to which the control signal is supplied, and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line. ## Claims ### Claim 1 A semiconductor device comprising: a bias line to which a bias current flows; a switch circuit controlling an amount of the bias current based on a control signal; a control line to which the control signal is supplied; and a cancellation circuit substantially cancelling a potential fluctuation of the bias line caused by changing the control signal, the potential fluctuation propagating via a parasitic capacitance between the control line and the bias line. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the cancellation circuit includes a balance capacity having one end being coupled to the bias line and the other end to which an inversion signal of the control signal is supplied. ### Claim 3 (depends on 2) The semiconductor device as claimed in claim 2, wherein the switch circuit comprises a first MOS transistor, and the parasitic capacitance comprises a capacitance between a gate electrode and a drain of the first MOS transistor. ### Claim 4 (depends on 3) The semiconductor device as claimed in claim 3, wherein the balance capacity comprises a second MOS transistor having source and drain short-circuited to each other. ### Claim 5 (depends on 4) The semiconductor device as claimed in claim 4, wherein a gate area of the second MOS transistor is substantially half as large as a gate area of the first MOS transistor. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, further comprising: a current-to-voltage conversion circuit converting the bias current into a bias voltage; and a bias transistor having a control electrode to which the bias voltage is supplied. ### Claim 7 (depends on 6) The semiconductor device as claimed in claim 6, further comprising a clock transmission line transmitting a clock signal, wherein the bias transistor is coupled to the clock transmission line so that transmission characteristics of the clock transmission line is controlled based on the bias voltage. ### Claim 8 (depends on 6) The semiconductor device as claimed in claim 6, further comprising an inverter array transmitting a clock signal, wherein the bias transistor is inserted between the inverter array and a power supply line so that transmission characteristics of the inverter array is controlled based on the bias voltage. ### Claim 9 A semiconductor device comprising: a bias line to which a bias current flows; a switch circuit including a plurality of MOS transistors each having a gate electrode and a drain, each of the gate electrodes having a different width from each other, and the drains being commonly coupled to the bias line; a control circuit supplying each of control signals to the gate electrode of an associated one of the MOS transistors; and a plurality of balance capacities each having a different capacitance from each other, and each having one end being commonly coupled to the bias line and the other end to which an inversion signal of an associated one of the control signals is supplied. ### Claim 10 (depends on 9) The semiconductor device as claimed in claim 9, wherein each of capacitances between the gate electrodes and the drains of the MOS transistors is substantially equal to a capacitance of one of the balance capacities to which an inversion signal of the associated one of the control signals is supplied.