# US 2014/0152375 A1 · Multiplexer and dynamic bias switch thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152375 A1 - Document ID: US20140152375A1 - Status: Published application - Kind: A1 - Application number: 13/705,104 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Himax Technologies Limited - Applicants: Himax Technologies Limited - Inventors: Wei-Kai Tseng - Web page: https://patentgrep.com/patent/US20140152375A1 ## CPC - H03K 17/693: Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A multiplexer and a dynamic bias switch thereof are provided. The dynamic bias switch includes a switch transistor and a dynamic bulk bias (DBB) unit. A first terminal and a second terminal of the switch transistor are respectively coupled to a first terminal and a second terminal of the dynamic bias switch. A bulk of the switch transistor is coupled to the DBB unit. The DBB unit selectively couples the first terminal or the second terminal of the switch transistor to the bulk of the switch transistor. ## Claims ### Claim 1 A multiplexer, comprising: a first switch, having a first terminal and a second terminal respectively coupled to a first port and a second port of the multiplexer; a second switch, having a first terminal and a second terminal respectively coupled to a third port and the second port of the multiplexer; a third switch, having a first terminal and a second terminal respectively coupled to the first port and a fourth port of the multiplexer; and a fourth switch, having a first terminal and a second terminal respectively coupled to the third port and the fourth port of the multiplexer; wherein at least one of the first switch, the second switch, the third switch and the fourth switch is a dynamic bias switch, the dynamic bias switch comprises a first switch transistor and a dynamic bulk bias (DBB) unit, a first terminal and a second terminal of the first switch transistor are respectively coupled to the first terminal and the second terminal of the dynamic bias switch, a bulk of the first switch transistor is coupled to the DBB unit, and the DBB unit selectively couples the first terminal or the second terminal of the first switch transistor to the bulk of the first switch transistor. ### Claim 2 (depends on 1) The multiplexer according to claim 1, wherein the second switch and the third switch are turned off and the fourth switch is turned on when the first switch is turned on; and the second switch and the third switch are turned on and the fourth switch is turned off when the first switch is turned off. ### Claim 3 (depends on 1) The multiplexer according to claim 1, wherein the DBB unit comprises: a first bias transistor, having a first terminal coupled to the first terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the second terminal of the first switch transistor; and a second bias transistor, having a first terminal coupled to the second terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the first terminal of the first switch transistor. ### Claim 4 (depends on 3) The multiplexer according to claim 3, wherein bulks of the first bias transistor and the second bias transistor are both coupled to the bulk of the first switch transistor. ### Claim 5 (depends on 3) The multiplexer according to claim 3, wherein conduction types of the first bias transistor, the second bias transistor and the first switch transistor are the same. ### Claim 6 (depends on 1) The multiplexer according to claim 1, wherein the dynamic bias switch further comprises: a second switch transistor, having a first terminal and a second terminal respectively coupled to the first terminal and the second terminal of the dynamic bias switch, wherein a bulk of the second switch transistor is coupled to the DBB unit, and the DBB unit further selectively couples the first terminal or the second terminal of the second switch transistor to the bulk of the second switch transistor. ### Claim 7 (depends on 6) The multiplexer according to claim 6, wherein the DBB unit comprises: a first bias transistor, having a first terminal coupled to the first terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the second terminal of the first switch transistor; a second bias transistor, having a first terminal coupled to the second terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the first terminal of the first switch transistor; a third bias transistor, having a first terminal coupled to the first terminal of the second switch transistor, a second terminal coupled to the bulk of the second switch transistor, and a control terminal coupled to the second terminal of the second switch transistor; and a fourth bias transistor, having a first terminal coupled to the second terminal of the second switch transistor, a second terminal coupled to the bulk of the second switch transistor, and a control terminal coupled to the first terminal of the second switch transistor. ### Claim 8 (depends on 7) The multiplexer according to claim 7, wherein bulks of the first bias transistor and the second bias transistor are both coupled to the bulk of the first switch transistor, and bulks of the third bias transistor and the fourth bias transistor are both coupled to the bulk of the second switch transistor. ### Claim 9 (depends on 7) The multiplexer according to claim 7, wherein a conduction type of the first switch transistor is different from a conduction type of the second switch transistor, and conduction types of the first bias transistor, the second bias transistor and the first switch transistor are the same, and conduction types of the third bias transistor, the fourth bias transistor and the second switch transistor are the same. ### Claim 10 (depends on 1) The multiplexer according to claim 1, wherein the DBB unit couples the bulk of the first switch transistor to one of the first terminal and the second terminal of the first switch transistor which has a higher voltage level when the first switch transistor is a P conduction type, and the DBB unit couples the bulk of the first switch transistor to one of the first terminal and the second terminal of the first switch transistor which has a lower voltage level when the first switch transistor is an N conduction type. ### Claim 11 A dynamic bias switch, comprising: a first switch transistor, having a first terminal and a second terminal respectively coupled to a first terminal and a second terminal of the dynamic bias switch; and a DBB unit, coupled to a bulk of the first switch transistor, and selectively coupling the first terminal or the second terminal of the first switch transistor to the bulk of the first switch transistor. ### Claim 12 (depends on 11) The dynamic bias switch according to claim 11, wherein the DBB unit comprises: a first bias transistor, having a first terminal coupled to the first terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the second terminal of the first switch transistor; and a second bias transistor, having a first terminal coupled to the second terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the first terminal of the first switch transistor. ### Claim 13 (depends on 12) The dynamic bias switch according to claim 12, wherein bulks of the first bias transistor and the second bias transistor are both coupled to the bulk of the first switch transistor. ### Claim 14 (depends on 12) The dynamic bias switch according to claim 12, wherein conduction types of the first bias transistor, the second bias transistor and the first switch transistor are the same. ### Claim 15 (depends on 11) The dynamic bias switch according to claim 11 further comprising: a second switch transistor, having a first terminal and a second terminal respectively coupled to the first terminal and the second terminal of the dynamic bias switch, wherein a bulk of the second switch transistor is coupled to the DBB unit, and the DBB unit further selectively couples the first terminal or the second terminal of the second switch transistor to the bulk of the second switch transistor. ### Claim 16 (depends on 15) The dynamic bias switch according to claim 15, wherein the DBB unit comprises: a first bias transistor, having a first terminal coupled to the first terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the second terminal of the first switch transistor; a second bias transistor, having a first terminal coupled to the second terminal of the first switch transistor, a second terminal coupled to the bulk of the first switch transistor, and a control terminal coupled to the first terminal of the first switch transistor; a third bias transistor, having a first terminal coupled to the first terminal of the second switch transistor, a second terminal coupled to the bulk of the second switch transistor, and a control terminal coupled to the second terminal of the second switch transistor; and a fourth bias transistor, having a first terminal coupled to the second terminal of the second switch transistor, a second terminal coupled to the bulk of the second switch transistor, and a control terminal coupled to the first terminal of the second switch transistor. ### Claim 17 (depends on 16) The dynamic bias switch according to claim 16, wherein bulks of the first bias transistor and the second bias transistor are both coupled to the bulk of the first switch transistor, and bulks of the third bias transistor and the fourth bias transistor are both coupled to the bulk of the second switch transistor. ### Claim 18 (depends on 16) The dynamic bias switch according to claim 16, wherein a conduction type of the first switch transistor is different from a conduction type of the second switch transistor, conduction types of the first bias transistor, the second bias transistor and the first switch transistor are the same, and conduction types of the third bias transistor, the fourth bias transistor and the second switch transistor are the same. ### Claim 19 (depends on 11) The dynamic bias switch according to claim 11, wherein the DBB unit couples the bulk of the first switch transistor to one of the first terminal and the second terminal of the first switch transistor which has a higher voltage level when the first switch transistor is a P conduction type; and the DBB unit couples the bulk of the first switch transistor to one of the first terminal and the second terminal of the first switch transistor which has a lower voltage level when the first switch transistor is an N conduction type.