# US 2014/0152372 A1 · Semiconductor integrated circuit and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152372 A1 - Document ID: US20140152372A1 - Status: Published application - Kind: A1 - Application number: 13/974,763 - Filed: 2013-08-23 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Hoi Jin LEE - Web page: https://patentgrep.com/patent/US20140152372A1 ## CPC - G06F 1/324: by lowering clock frequency - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A semiconductor integrated circuit and a method operating the same are provided. The semiconductor integrated circuit includes a first clock network configured to divide a clock signal into first output clock signals with a high frequency, a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency, a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to output one of the first output clock signals and the second output clock signals, according to a power mode, and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits. ## Claims ### Claim 1 A method of operating a semiconductor integrated circuit, the method comprising: dividing a clock signal into first output clock signals with a high frequency; dividing the clock signal into second output clock signals with a non-high frequency; and selecting and sinking one of the first output clock signals and the second output clock signals, according to a power mode. ### Claim 2 (depends on 1) The method of claim 1, wherein the first output clock signals are generated by driving the clock signal to a first clock network configured in a mesh structure. ### Claim 3 (depends on 2) The method of claim 2, wherein the second output clock signals are generated by driving the clock signal to a second clock network configured in a mesh structure with less density than the mesh structure of the first clock network. ### Claim 4 (depends on 2) The method of claim 2, wherein the second output clock signals are generated by driving the clock signal to a second clock network configured in a tree structure with less density than the mesh structure of the first clock network. ### Claim 5 (depends on 1) The method of claim 1, wherein the power mode comprises a maximum performance mode and a non-maximum performance mode, the first output clock signals are selected and sunk in the maximum performance mode, and the second output clock signals are selected and sunk in the non-maximum performance mode. ### Claim 6 A semiconductor integrated circuit comprising: a first clock network configured to divide a clock signal into first output clock signals with a high frequency; a second clock network configured to divide the clock signal into second output clock signals with a non-high frequency; a plurality of selection circuits configured to be connected between the first clock network and the second clock network, and configured to select and output one of the first output clock signals and the second output clock signals, according to a power mode; and a plurality of clock sinks configured to sink output clock signals respectively output from the selection circuits. ### Claim 7 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the first clock network is configured in a mesh structure, and the second clock network is configured in a mesh structure with less density than the mesh structure of the first clock network. ### Claim 8 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the first clock network is configured in a mesh structure, and the second clock network is configured in a tree structure with less density than the mesh structure of the first clock network. ### Claim 9 (depends on 6) The semiconductor integrated circuit of claim 6, wherein each of the selection circuits is a NOR gate circuit configured to receive one of the first output clock signals and one of the second output clock signals, and one of the first clock network and the second clock network, which is not selected according to the power mode, is fixed to a ground voltage. ### Claim 10 (depends on 6) The semiconductor integrated circuit of claim 6, wherein each of the selection circuits is a NAND gate circuit configured to receive one of the first output clock signals and one of the second output clock signals, and one of the first clock network and the second clock network, which is not selected according to the power mode, is fixed to a supply voltage. ### Claim 11 (depends on 6) The semiconductor integrated circuit of claim 6, wherein each of the clock sinks is a flip-flop configured to output a data signal in response to the respective output clock signal output from a respective selection circuit. ### Claim 12 (depends on 6) The semiconductor integrated circuit of claim 6, further comprising a power mode detector configured to monitor the power mode of the semiconductor integrated circuit, and configured to output a selection signal, wherein each of the selection circuits is a multiplexer configured to output one of the first output clock signals and the second output clock signals, according to the selection signal. ### Claim 13 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the first clock network and the second clock network are positioned on different layers. ### Claim 14 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the first clock network and the second clock network are positioned on a same layer. ### Claim 15 (depends on 6) The semiconductor integrated circuit of claim 6, wherein the selection circuits select the first clock network when the power mode is a maximum performance mode, and select the second clock network when the power mode is a non-maximum performance mode. ### Claim 16 A semiconductor integrated circuit comprising: a first clock network configured in a mesh structure to generate first output clock signals; a second clock network configured in a tree structure to generate second output clock signals; a plurality of selection circuits configured to receive the first output clock signals and the second output clock signals, each of the selection circuits is configured to select and output one of the first output clock signals or one of the second output clock signals, according to a power mode; and a plurality of clock sinks configured to receive the one of the first output clock signals or one of the second output clock signals from respective selection circuits, each of the clock sinks is configured to sink the one of the first output clocks signals or one of the second output signals output from a respective selection circuit, wherein the plurality of selection circuits is further configured to be connected between the first clock network and the second clock network. ### Claim 17 (depends on 16) The semiconductor integrated circuit of claim 16, wherein the first output clock signals and the second output clock signals are generated from a common clock signal. ### Claim 18 (depends on 16) The semiconductor integrated circuit of claim 16, wherein the selection circuits select one of the first output clock signals when the power mode is a maximum performance mode, and selects one of the second output clock signals when the power mode is a non-maximum performance mode. ### Claim 19 (depends on 16) The semiconductor integrated circuit of claim 16, wherein each of the plurality of selection circuits is further configured as a NAND circuit, such that one of the first clock network and the second clock network, which is not selected by the selection circuits, is fixed to a supply voltage. ### Claim 20 (depends on 16) The semiconductor integrated circuit of claim 16, wherein each of the plurality of selection circuits is further configured as a NOR circuit, such that one of the first clock network and the second clock network, which is not selected by the selection circuits, is fixed to a ground voltage.