# US 2014/0152371 A1 · High linearity mixer using a 33% duty cycle clock for unwanted harmonic suppression

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- Number: US 2014/0152371 A1
- Document ID: US20140152371A1
- Status: Published application
- Kind: A1
- Application number: 14/177,236
- Filed: 2014-02-11
- Published: 2014-06-05
- Earliest claimed: 2012-03-30
- Assignees: MediaTek Singapore Pte. Ltd.
- Applicants: MediaTek Singapore Pte. Ltd.
- Inventors: Ankush Goel; Neric Fong
- Web page: https://patentgrep.com/patent/US20140152371A1

## CPC

- H03D 7/1475: {Subharmonic mixer arrangements}
- H03B 1/04: Reducing undesired oscillations, e.g. harmonics
- H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)}
- H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential}
- H03D 7/165: {at least two frequency changers being located in different paths, e.g. in two paths with carriers in quadrature (combined with amplitude demodulation H03D1/2245, combined with angle demodulation H03D3/007; N-path filters H03H19/002)}
- H03D 2200/0086: Reduction or prevention of harmonic frequencies
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)
- H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H)

## Abstract

One mixer circuit includes mixer elements having 3N pairs of differential inputs. There are non-overlapping clock signals provided to the mixer elements which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. Output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals. Another mixer circuit includes a first mixer element and a signal combining device. The first mixer element has 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33⅓ percent, and N is a positive integer. The signal combining device combines outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals.

## Claims

### Claim 1

A mixer circuit comprising:
a plurality of mixer elements comprising 3N pairs of differential inputs, wherein there are non-overlapping clock signals provided to the plurality of mixer elements which have a duty cycle equal to or less than 33⅓ percent, wherein N is a positive integer;
wherein output differential signals of the mixer elements do not contain third order harmonic content of the non-overlapping clock signals.

### Claim 2 (depends on 1)

The mixer circuit of claim 1, wherein IQ inputs to one of the plurality of mixer elements are symmetric with that to another of the mixer elements.

### Claim 3 (depends on 1)

The mixer circuit of claim 1, wherein the plurality of mixer elements are passive mixers.

### Claim 4 (depends on 1)

The mixer circuit of claim 1, wherein the plurality of mixer elements comprises sets of differential switches.

### Claim 5 (depends on 1)

The mixer circuit of claim 1, wherein the 3N pairs of differential inputs comprises:
one pair of differential in-phase inputs for driving one pair of differential output signals by one pair of the non-overlapping clock signals; and
two pairs of differential quadrature inputs for driving two pairs of differential output signals by two pairs of the non-overlapping clock signals, respectively;
wherein polarities and phases of the one pair of differential in-phase inputs and the two pairs of differential quadrature inputs are configured such that unwanted image signals are suppressed at an output of the mixer circuit.

### Claim 6 (depends on 5)

The mixer circuit of claim 5, further comprising:
a plurality of scaling amplifiers for scaling amplitudes of the one pair of differential in-phase inputs and two pairs of differential quadrature inputs before the mixer elements.

### Claim 7 (depends on 1)

The mixer circuit of claim 1, wherein the non-overlapping clock signals are provided by a divide-by-3 phase generation circuit.

### Claim 8 (depends on 1)

The mixer circuit of claim 1, wherein the mixer elements comprises a first mixer element comprising one pair of differential in-phase inputs for driving one pair of differential output signals and two pairs of differential quadrature inputs for driving two pairs of differential output signals; and
a second mixer element comprising one pair of differential quadrature inputs for driving one pair of differential output signals and two pairs of differential in-phase inputs for driving two pairs of differential output signals;
wherein polarities and phases of the differential in-phase inputs and quadrature inputs of the first and second mixers are configured such that unwanted image signals is suppressed at an output of the mixer circuit.

### Claim 9 (depends on 8)

The mixer circuit of claim 8, further comprising:
first and second drivers coupled to the differential outputs of the first and second mixer elements to provide the differential output signals;
wherein positive outputs of the first and second drivers are combined and negative outputs of the first and second drivers are combined;
wherein the first and second drivers provide reverse isolation for the first and second mixer elements.

### Claim 10 (depends on 8)

The mixer circuit of claim 8, further comprising:
a third mixer element comprising one pair of differential in-phase inputs for driving one pair of differential output signals and two pairs of differential quadrature inputs for driving two pairs of differential output signals; and
a fourth mixer element comprising one pair of differential quadrature inputs for driving one pair of differential output signals and two pairs of differential in-phase inputs for driving two pairs of differential output signals;
wherein the polarities and the phases of the differential inputs and quadrature inputs of the third and fourth mixers are configured such that unwanted image signals and even order harmonics of the signals are suppressed at the output of the mixer circuit.

### Claim 11 (depends on 10)

The mixer circuit of claim 10, further comprising:
first and second drivers coupled to the differential outputs of the first and second mixer elements, and third and fourth drivers coupled to differential outputs of the third and fourth mixer elements, respectively, to provide the differential output signals.

### Claim 12 (depends on 11)

The mixer circuit of claim 11, wherein positive outputs of the first, second drivers, and negative outputs of the third and fourth drivers are combined so that the fundamental harmonic of the output signal is constructively added, while the second harmonic of the output signal is cancelled.

### Claim 13 (depends on 11)

The mixer circuit of claim 11, wherein the first, second, third and fourth drivers provide reverse isolation for the first, second, third and fourth mixer elements.

### Claim 14

A mixer circuit comprising:
a first mixer element comprising 3N pairs of differential inputs, wherein there are a plurality of non-overlapping clock signals provided to the first mixer element which have a duty cycle equal to or less than 33⅓ percent, wherein N is a positive integer; and
a signal combining device coupled to the first mixer element, arranged to combine outputs from the first mixer element wherein an output signal of the signal combining device do not contain third order harmonic content of the non-overlapping clock signals.

### Claim 15 (depends on 14)

The mixer circuit of claim 14, further comprising at least one other mixer element coupled to the signal combining device, wherein a plurality of non-overlapping clock signals are provided to the at least one other mixer element which have a duty cycle equal to or less than 33⅓ percent.