# US 2014/0152369 A1 · Level Translator Circuit, Driving Circuit for Driving High-Voltage Device and Method Thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152369 A1 - Document ID: US20140152369A1 - Status: Published application - Kind: A1 - Application number: 14/097,085 - Filed: 2013-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: iWatt Integrated Circuits Technology (Tianjin) Limited - Applicants: iWatt Integrated Circuits Technology (Tianjin) Limited - Inventors: Wei Qi - Web page: https://patentgrep.com/patent/US20140152369A1 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 3/35613: {the input circuit having a differential configuration} - H03K 19/018528: {with at least one differential stage} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present invention provides a level translator circuit, a driving circuit for driving a high-voltage device and a corresponding method. The driving circuit for driving a high-voltage device comprises: a zener diode whose cathode is connected to a high-voltage power supply voltage and whose anode is connected to a ground potential of a low-voltage domain through a resistor; a high-voltage PMOS transistor whose gate is connected to an anode of the resistor, whose drain is connected to the ground potential of the low-voltage domain, and whose source is operable to supply a ground potential of a high-voltage domain; a level translator operable to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain and output the second signal; and a low-voltage driving circuit operable to receive the second signal and adapt the second signal as a third signal which can drive the high-voltage device. The present invention allows for use of the low-voltage device to drive the high-voltage device to achieve the drive of the high-voltage device in a simple and efficient manner. ## Claims ### Claim 1 A driving circuit for driving a high-voltage device, comprising: a zener diode whose cathode is connected to a high-voltage power supply voltage and whose anode is connected to a ground potential of a low-voltage domain through a resistor; a high-voltage PMOS transistor whose gate is connected to an anode of the resistor, whose drain is connected to the ground potential of the low-voltage domain, and whose source is operable to supply a ground potential of a high-voltage domain; a level translator whose working voltage terminal is connected to the high-voltage power supply voltage, whose first grounded terminal is connected to the ground potential of the low-voltage domain, and whose second grounded terminal is connected to the ground potential of the high-voltage domain, the level translator being operable to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain and output the second signal; and a low-voltage driving circuit connected between the high-voltage power supply voltage and the ground potential of the high-voltage domain, and being operable to receive the second signal and adapt the second signal as a third signal which can drive the high-voltage device. ### Claim 2 (depends on 1) The driving circuit according to claim 1, wherein the low-voltage driving circuit comprises: a low-voltage PMOS transistor and a low-voltage NMOS transistor, their gates being connected together to receive the second signal, their drains being connected together to provide the third signal, a source of the low-voltage PMOS transistor being connected to the high-voltage power supply voltage, and a source of the low-voltage NMOS transistor being connected to the ground potential of the high-voltage domain. ### Claim 3 (depends on 1) The driving circuit according to claim 1, wherein the low-voltage driving circuit comprises a low-voltage operational amplifier circuit whose input terminal is used to receive the second signal and whose output terminal is used to provide the third signal. ### Claim 4 (depends on 2, 3) The driving circuit according to claim 2 or 3, further comprising: a high-voltage PMOS transistor and a high-voltage NMOS transistor, a source of the high-voltage PMOS transistor and a source of the high-voltage NMOS transistor being respectively connected to the high-voltage power supply voltage and the ground potential of the low-voltage domain, a gate of the high-voltage PMOS transistor being used to receive the third signal, a gate of the high-voltage NMOS transistor being used to receive the first signal, and a drain of the high-voltage PMOS transistor and a drain of the high-voltage NMOS transistor being connected together to provide a fourth signal. ### Claim 5 (depends on 4) The driving circuit according to claim 4, wherein a variation range of the first signal is between 0 volt and 5 volts, a variation range of the second signal and the third signal is between the high-voltage power supply voltage minus 5 volts and the high-voltage power supply voltage, and a variation range of the fourth signal is between 0 volt and the high-voltage power supply voltage. ### Claim 6 (depends on 1, 2, 3) The driving circuit according to any one of claims 1-3, wherein the high-voltage power supply voltage is 100 volts or any predetermined voltage value below 100 volts. ### Claim 7 (depends on 6) The driving circuit according to claim 6, wherein the high-voltage power supply voltage is one of 8 volts, 12 volts, 20 volts, 24 volts and 48 volts. ### Claim 8 (depends on 1) The driving circuit according to claim 1, wherein the level translator comprises a plurality of switching elements. ### Claim 9 (depends on 1) The driving circuit according to claim 1, wherein the level translator comprises a first inverter and a second inverter which are connected in series, wherein the first inverter works between the high-voltage power supply voltage and the ground potential of the low-voltage domain to receive the first signal; and wherein the second inverter works between the high-voltage power supply voltage and the ground potential of the high-voltage domain to provide the second signal. ### Claim 10 A method of driving a high-voltage device, comprising: providing a ground potential of a high-voltage domain by using a zener diode, a high-voltage PMOS transistor and a resistor, wherein a cathode of the zener diode is connected to a high-voltage power supply voltage, and an anode of the zener diode is connected to a ground potential of a low-voltage domain through the resistor, and wherein a gate of the high-voltage PMOS transistor is connected to an anode of the resistor, and an drain thereof is connected to the ground potential of the low-voltage domain, and a source thereof is operable to supply the ground potential of the high-voltage domain; using a level translator to convert a first signal in the low-voltage domain as received to a second signal in the high-voltage domain, wherein a working voltage terminal of the level translator is connected to the high-voltage power supply voltage, a first grounded terminal of the level translator is connected to the ground potential of the low-voltage domain, and a second grounded terminal of the level translator is connected to the ground potential of the high-voltage domain; and using a low-voltage drive circuit to adapt the second signal as a third signal which can drive the high-voltage device. ### Claim 11 (depends on 10) The method according to claim 10, wherein the low-voltage driving circuit comprises: a low-voltage PMOS transistor and a low-voltage NMOS transistor, their gates being connected together to receive the second signal, their drains are connected together to provide the third signal, a source of the low-voltage PMOS transistor being connected to the high-voltage power supply voltage, and a source of the low-voltage NMOS transistor being connected to the ground potential of the high-voltage domain. ### Claim 12 (depends on 10) The method according to claim 10, wherein the low-voltage driving circuit comprises a low-voltage operational amplifier circuit whose input terminal is used to receive the second signal and whose output terminal is used to provide the third signal. ### Claim 13 (depends on 11, 12) The method according to claim 11 or 12, further comprising: using a high-voltage PMOS transistor and a high-voltage NMOS transistor connected in series to provide a fourth signal based on the first signal and the third signal, wherein a source of the high-voltage PMOS transistor and a source of the high-voltage NMOS transistor are respectively connected to the high-voltage power supply voltage and the ground potential of the low-voltage domain, a gate of the high-voltage PMOS transistor is used to receive the third signal, a gate of the high-voltage NMOS transistor is used to receive the first signal, and a drain of the high-voltage PMOS transistor and a drain of the high-voltage NMOS transistor are connected together to provide the fourth signal. ### Claim 14 (depends on 13) The method according to claim 13, wherein a variation range of the first signal is between 0 volt and 5 volts, a variation range of the second signal and the third signal is between the high-voltage power supply voltage minus 5 volts and the high-voltage power supply voltage, and a variation range of the fourth signal is between 0 volt and the high-voltage power supply voltage. ### Claim 15 (depends on 10, 11, 12) The method according to any one of claims 10-12, wherein the high-voltage power supply voltage is 100 volts or any predetermined voltage value below 100 volts.