# US 2014/0152362 A1 · Duty Cycle Adjusting Circuit and Adjusting Method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152362 A1 - Document ID: US20140152362A1 - Status: Published application - Kind: A1 - Application number: 14/097,114 - Filed: 2013-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: iWatt Integrated Circuits Technology (Tianjin) Limited - Applicants: iWatt Integrated Circuits Technology (Tianjin) Limited - Inventors: Xiaogang Zhao - Web page: https://patentgrep.com/patent/US20140152362A1 ## CPC - H03K 3/017: Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present invention relates to a square wave generator circuit, an integrated circuit, a DC/DC converter and an AC/DC converter. The square wave generator circuit comprises a first mirror current branch which is connected with ground via a first switching element and a first capacitor in parallel with the first switching element, wherein the first switching element is operable to be opened or closed periodically under control of a first clock signal so as to generate a first sawtooth wave signal at a non-grounded terminal of the first capacitor; a second mirror current branch which is connected with ground via a second switching element and a second capacitor in parallel with the second switching element, wherein the second switching element is operable to be opened or closed periodically under control of a second clock signal synchronous with the first clock signal so as to generate a second sawtooth wave signal at a non-grounded terminal of the second capacitor; and a comparator, one input terminal of which is connected to the non-grounded terminal of the first capacitor and the other input terminal of which is connected to the non-grounded terminal of the second capacitor, so that a square wave signal can be outputted at an output terminal of the comparator, wherein a duty cycle of the square wave signal depends on a ratio of a capacitance of the second capacitor to a capacitance of the first capacitor. ## Claims ### Claim 1 A square wave generator circuit, comprising: a first mirror current branch which is connected with ground via a first switching element and a first capacitor in parallel with the first switching element, wherein the first switching element is operable to be opened or closed periodically under control of a first clock signal so as to generate a first sawtooth wave signal at a non-grounded terminal of the first capacitor; a second mirror current branch which is connected with ground via a second switching element and a second capacitor in parallel with the second switching element, wherein the second switching element is operable to be opened and closed periodically under control of a second clock signal synchronous with the first clock signal so as to generate a second sawtooth wave signal at a non-grounded terminal of the second capacitor; and a comparator, one input terminal of which is connected to the non-grounded terminal of the first capacitor and the other input terminal of which is connected to the non-grounded terminal of the second capacitor, so that a square wave signal can be outputted at an output terminal of the comparator, wherein a duty cycle of the square wave signal depends on a ratio of a capacitance of the second capacitor to a capacitance of the first capacitor. ### Claim 2 (depends on 1) The square wave generator circuit according to claim 1, wherein the ratio of the capacitance of the second capacitor to the capacitance of the first capacitor is greater than one, and wherein the duty cycle of the square wave signal reduces as the ratio increases. ### Claim 3 (depends on 2) The square wave generator circuit according to claim 2, wherein an in-phase input terminal of the comparator is connected to the non-grounded terminal of the second capacitor and an anti-phase input terminal of the comparator is connected to the non-grounded terminal of the first comparator. ### Claim 4 (depends on 3) The square wave generator circuit according to claim 3, wherein the first clock signal is a square wave signal having a duty cycle 50%, and the second clock signal is a square wave signal generated based on the first clock signal and having a duty cycle less than 4%. ### Claim 5 (depends on 4) The square wave generator circuit according to claim 4, wherein the second clock signal has a duty cycle less than 1%. ### Claim 6 (depends on 4) The square wave generator circuit according to claim 4, further comprising a signal clock converting circuit which comprises: a first inverter, a second inverter and a third inverter connected in series, an input terminal of the first inverter being operable to receive the first clock signal; a capacitor, one terminal of which is connected to an output terminal of the first inverter and the other terminal of which is grounded; an AND gate, one input terminal of which is connected to an output terminal of the third inverter and the other input terminal of which is connected to the input terminal of the first inverter so that the second clock signal is outputted at an output terminal of the AND gate. ### Claim 7 (depends on 4) The square wave generator circuit according to claim 4, wherein the duty cycle of the square wave signal outputted by the comparator is equal to 1/[2*(1−1/n)], wherein n is the ratio of the capacitance of the second capacitor to the capacitance of the first capacitor, and n is greater than 2. ### Claim 8 (depends on 1) The square wave generator circuit according to claim 1, further comprising: a third switching element connected between the first mirror current branch and the first switching element, the third switching element and the first switching element being operable to be opened and closed alternately under control of the first clock signal; and a fourth switching element connected between the second mirror current branch and the second switching element, the fourth switching element and the second switching element being operable to be opened and closed alternately under control of the second clock signal. ### Claim 9 (depends on 8) The square wave generator circuit according to claim 8, wherein the first mirror current branch comprises a first P-MOS transistor, the second mirror current branch comprises a second P-MOS transistor, a gate of the first P-MOS transistor and a gate of the second P-MOS transistor are both connected to a gate of a reference P-MOS transistor, a source of the first P-MOS transistor and a source of the second P-MOS transistor are both connected to an operation voltage of the square wave generator circuit, a source of the reference P-MOS transistor is connected to the operation voltage, the gate of the reference P-MOS transistor is connected to a drain thereof, a drain of the reference P-MOS transistor is grounded via a constant current source; and wherein the reference P-MOS transistor, the first P-MOS transistor and the second P-MOS transistor have the same properties. ### Claim 10 (depends on 9) The square wave generator circuit according to claim 9, wherein the first switching element comprises a first N-MOS transistor, the second switching element comprises a second N-MOS transistor, the third switching element comprises a third P-MOS transistor, the fourth switching element comprises a fourth P-MOS transistor, and wherein a source of the first N-MOS transistor is grounded, and a drain and a gate of the first N-MOS transistor are respectively connected to a drain and a gate of the third P-MOS transistor, a source of the third P-MOS transistor is connected to a drain of the first P-MOS transistor, a source of the second N-MOS transistor is grounded and a drain and a gate of the second N-MOS transistor are respectively connected to a drain and a gate of the fourth P-MOS transistor, and a source of the fourth P-MOS transistor is connected to a drain of the second P-MOS transistor. ### Claim 11 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10) The square wave generator circuit according to any one of claims 1-10, further comprising an OR gate which performs a logical OR operation on the square wave signal outputted by the comparator and the first clock signal to output another square wave signal. ### Claim 12 (depends on 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11) An integrated circuit comprising the square wave generator circuit according to any one of claims 1-11. ### Claim 13 (depends on 12) A DC/DC converter, comprising the integrated circuit according to claim 12. ### Claim 14 (depends on 12) An AC/DC converter, comprising the integrated circuit according to claim 12.