# US 2014/0152361 A1 · Apparatus and methods for altering the timing of a clock signal > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152361 A1 - Document ID: US20140152361A1 - Status: Published application - Kind: A1 - Application number: 14/172,441 - Filed: 2014-02-04 - Published: 2014-06-05 - Earliest claimed: 2011-06-02 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Yantao Ma; Aaron Willey - Web page: https://patentgrep.com/patent/US20140152361A1 ## CPC - H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125) - H03K 19/00361: {in field effect transistor circuits} - H03K 19/00369: {Modifications for compensating variations of temperature, supply voltage or other physical parameters} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Clock signal timing cells, clock signal timing circuits, clock circuits, memory devices, systems, and method for altering the timing of a clock signal are disclosed. An example method for altering the timing of an output signal provided responsive to an input clock signal includes adjusting a transition of an edge of the output signal from one voltage level to another based at least in part on a bias signal. An example clock signal timing cell includes an inverter and a bias controlled inverter coupled in parallel to the inverter. The bias controlled circuit is configured to provide an output signal wherein a transition of a clock edge of the output signal between first and second voltage levels is based at least in part on a bias signal. ## Claims ### Claim 1 A method comprising: receiving an input clock signal at a bias controlled inverter and an inverter, the inverter having a lower drive strength than the bias inverter; adjusting, at the bias controlled inverter, a transition of an edge of an output clock signal from one voltage level to another based at least in part on a bias signal, wherein the output clock signal is provided responsive to the input clock signal; and providing the output clock signal at an output of the inverter and the bias controlled inverter. ### Claim 2 (depends on 1) The method of claim 1, wherein adjusting the transition of an edge of the output clock signal comprises adjusting a drive strength of the bias controlled inverter. ### Claim 3 (depends on 2) The method of claim 2, wherein adjusting the drive strength of the bias controlled inverter comprises adjusting a conductivity of a transistor coupled to a supply voltage in the bias controlled inverter. ### Claim 4 (depends on 2) The method of claim 2, wherein adjusting the drive strength of the bias controlled inverter comprises adjusting a conductivity of a transistor coupled to a reference voltage in the bias controlled inverter. ### Claim 5 (depends on 1) The method of claim 1, further comprising generating the bias signal based at least in part on a multi-bit control signal. ### Claim 6 (depends on 5) The method of claim 5, wherein each bit of the multi-bit control signal is configured to control a respective transistor in the bias controlled inverter. ### Claim 7 (depends on 1) The method of claim 1, wherein the bias controlled inverter is a first bias controlled inverter, the inverter is a first inverter, the output clock signal is a first output clock signal, and the bias signal is a first bias signal, and the method further comprises: adjusting at a second bias controlled inverter coupled in parallel with a second inverter, an edge of a second output clock signal from one voltage level to another based at least in part on a second bias signal, wherein the second output clock signal is provided responsive to the first output clock signal. ### Claim 8 (depends on 7) The method of claim 7, wherein adjusting the edge of the first output clock signal comprises adjusting a rising edge of the first output clock signal and wherein adjusting the edge of the second output clock signal comprises adjusting a falling edge of the second output clock signal. ### Claim 9 A method comprising: adjusting, at a first clock signal timing cell, a rising clock edge transition of an intermediate clock signal from a first voltage level to a second voltage level based at least in part on a first bias signal, the intermediate clock signal provided responsive to the input clock signal; and adjusting, at a second clock signal timing cell, a falling clock edge transition of an output clock signal from the second voltage level to the first voltage level based at least in part on a second bias signal, the output clock signal provided responsive to the intermediate clock signal. ### Claim 10 (depends on 9) The method of claim 9, further comprising: receiving the first bias signal at the first clock signal timing cell from a first bias circuit; and receiving the second bias signal at the second clock signal timing cell from a second bias circuit. ### Claim 11 (depends on 9) The method of claim 9, wherein adjusting the rising clock edge transition comprises adjusting the rate of the rising clock edge transition. ### Claim 12 (depends on 11) The method of claim 11, wherein adjusting the rate of the rising clock edge transition comprises adjusting a conductivity of a transistor coupling an inverter circuit to a supply voltage based at least in part on voltage of the first bias signal. ### Claim 13 (depends on 9) The method of claim 9, wherein adjusting the falling clock edge transition comprises adjusting the rate of the falling clock edge transition. ### Claim 14 (depends on 13) The method of claim 13, wherein adjusting the rate of the falling clock edge transition comprises adjusting a conductivity of a transistor coupling an inverter circuit to a reference voltage based at least in part on voltage of the second bias signal. ### Claim 15 (depends on 9) The method of claim 9, wherein the second bias signal comprises a complement of the first bias signal. ### Claim 16 (depends on 9) The method of claim 9, further comprising: adjusting a falling clock edge transition of the intermediate clock signal from the second voltage level to the first voltage level based at least in part on a third bias signal; and adjusting a rising clock edge transition of the output clock signal from the first voltage level to the second voltage level based at least in part on a fourth bias signal. ### Claim 17 An apparatus comprising: a first bias controlled clock timing cell configured to alter timing of a clock signal edge based on multi-bit signals, the first bias controlled clock timing cell including a bias controlled inverter coupled in parallel with an inverter having weaker drive strength than the bias controlled inverter; and a programmable controller configured to provide a multi-bit signal to the first bias controlled clock timing cell to control the bias controlled inverter. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the bias controlled inverter is configured to have a drive strength adjusted by the multi-bit signal. ### Claim 19 (depends on 18) The apparatus of claim 18, further comprising: a second bias controlled dock timing cell coupled in series with the first bias controlled clock timing cell and configured to favor altering the timing of a different clock signal edge than the first bias controlled dock timing cell. ### Claim 20 (depends on 17) The apparatus of claim 17, wherein the clock signal edge is a rising clock edge and the first bias controlled clock timing cell is further configured to alter timing of a falling clock edge. ### Claim 21 (depends on 17) The apparatus of claim 17, wherein the first bias controlled clock timing cell is configured to favor altering the timing of a rising clock edge and the second bias controlled dock timing cell is configured to favor altering the timing of a falling clock edge. ### Claim 22 (depends on 17) The apparatus of claim 17, wherein the multi-bit signal represents a multi-bit digital bias signal.