# US 2014/0152360 A1 · Phase difference quantization circuit, delay value control circuit thereof, and delay circuit

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- Number: US 2014/0152360 A1
- Document ID: US20140152360A1
- Status: Published application
- Kind: A1
- Application number: 14/093,356
- Filed: 2013-11-29
- Published: 2014-06-05
- Earliest claimed: 2011-12-29
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong-Suk SHIN
- Web page: https://patentgrep.com/patent/US20140152360A1

## CPC

- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03K 5/131: Digitally controlled
- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- H03K 2005/0028: {using varicaps, e.g. gate capacity of a FET with specially defined threshold, as delaying capacitors}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

## Claims

### Claim at position 1

1-4. (canceled)

### Claim 5

A phase difference quantization circuit comprising:
a path selection unit configured to transfer a first input signal to a first first-node and a second input signal to a first second-node in a normal mode and transfer the first input signal to the first first-node and the first second-node in a calibration mode;
a first phase comparison unit configured to compare a phase of a signal loaded on the first first-node and a phase of a signal loaded on the first second-node and generate a first up/down signal;
a first delay unit configured to transfer the signal loaded on the first first-node to a second first-node and the signal loaded on the first second-node to a second second-node, wherein the first delay unit is further configured to select one of the signal loaded on the first first-node and the signal loaded on the first second-node in response to the first up/down signal, delay the selected signal by a first delay value and transfer the delayed signal;
a second phase comparison unit configured to compare a phase of a signal loaded on the second first-node and a phase of a signal loaded on the second second-node and generate a second up/down signal;
a second delay unit configured to transfer the signal loaded on the second first-node to a third first-node and the signal loaded on the second second-node to a third second-node, wherein the second delay unit is further configured to select one of the signal loaded on the second first-node and the signal loaded on the second second-node in response to the second up/down signal, delay the selected signal by a second delay value and transfer the delayed signal;
a first replica delay unit replicating the second delay unit and configured to transfer a signal loaded on the third first-node to a third third-node and a signal loaded on the third second-node to a third fourth-node, wherein the first replica delay unit is further configured to select one of the signal loaded on the third first-node and the signal loaded on the third second-node in response to the second up/down signal, delay the selected signal by the second delay value and transfer the delayed signal;
a first delay control unit configured to compare a phase of a signal loaded on the third third-node and a phase of a signal loaded on the third fourth-node and control the second delay value of the second delay unit using a comparison result; and
a third phase comparison unit configured to compare a phase of the signal loaded on the third first-node and a phase of the signal loaded on the third second-node and generate a third up/down signal.

### Claim 6 (depends on 5)

The phase difference quantization circuit of claim 5, further comprising:
a third delay unit configured to transfer the signal loaded on the third first-node to a fourth first-node and the signal loaded on the third second-node to a fourth second-node, wherein the third delay unit is further configured to select one of the signal loaded on the third first-node and the signal loaded on the third second-node in response to the third up/down signal, delay the selected signal by a third delay value and transfer the delayed signal;
a second replica delay unit replicating the third delay unit and configured to transfer a signal loaded on the fourth first-node to a fourth third-node and a signal loaded on the fourth second-node to a fourth fourth-node, wherein the second replica delay unit is further configured to select one of the signal loaded on the fourth first-node and the signal loaded on the fourth second-node in response to the third up/down signal, delay the selected signal by the third delay value and transfer the delayed signal;
a second delay control unit configured to compare a phase of a signal loaded on the fourth third-node and a phase of a signal loaded on the fourth fourth-node and control the third delay value of the third delay unit using a comparison result; and
a fourth phase comparison unit configured to compare a phase of the signal loaded on the fourth first-node and a phase of the signal loaded on the fourth second-node and generate a fourth up/down signal.

### Claim 7 (depends on 6)

The phase difference quantization circuit of claim 6, wherein the first delay control unit and the second delay control unit are each configured to operate in the calibration mode and stop the operation in the normal mode.

### Claim 8 (depends on 6)

The phase difference quantization circuit of claim 6, wherein the first delay value is two times the second delay value and the second delay value is two times the third delay value.

### Claim 9 (depends on 6)

The phase difference quantization circuit of claim 6,
wherein the first delay control unit comprises:
a first calibrating phase comparing section configured to compare the phase of the signal loaded on the third third-node and the phase of the signal loaded on the third fourth-node and output a first calibrating up/down signal; and
a first control section configured to generate first delay codes for controlling the second delay value of the second delay unit and the first replica delay unit in response to the first calibrating up/down signal, and
wherein the second delay control unit comprises:
a second calibrating phase comparing section configured to compare the phase of the signal loaded on the fourth third-node and the phase of the signal loaded on the fourth fourth-node and output a second calibrating up/down signal; and
a second control section configured to generate second delay codes for controlling the third delay value of the third delay unit and the second replica delay unit in response to the second calibrating up/down signal.

### Claim at position 7

10-17. (canceled)