# US 2014/0152357 A1 · Methods and circuits for reducing clock jitter

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- Number: US 2014/0152357 A1
- Document ID: US20140152357A1
- Status: Published application
- Kind: A1
- Application number: 13/878,351
- Filed: 2011-10-03
- Published: 2014-06-05
- Earliest claimed: 2010-10-11
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Jared Zerbe; Teva Stone; Jihong Ren
- Web page: https://patentgrep.com/patent/US20140152357A1

## CPC

- H04L 7/02: Speed or phase control by the received code signals, the signals containing no special synchronisation information {(H04L7/0075 takes precedence)}
- H03K 5/1252: Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08)
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

## Claims

### Claim 1

An integrated circuit comprising:
a data sampler having a data input node, a data output node, and a clock node;
a data path extending to the data input node;
a clock path extending from a clock source to the clock node and including a linear equalizer, the linear equalizer having an equalization control port; and
equalization control circuitry coupled between the data output node and the equalization control port.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the equalizer is a linear equalizer.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein the equalizer is a continuous-time equalizer.

### Claim 4 (depends on 2)

The integrated circuit of claim 2, wherein the clock path further includes a clock buffer.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the clock buffer is a linear buffer.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein the clock buffer is a CML buffer.

### Claim 7 (depends on 1)

The integrated circuit or claim 1, wherein the equalization control port receives an offset signal that adjusts a voltage offset of the equalizer.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the control circuitry applies the offset signal for a first edge of a clock signal in the clock path to produce an equalized clock signal and removes the offset responsive to an edge of the equalized clock signal.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the linear equalizer is one of a plurality of linear equalizers selectively included in the clock path, wherein a number of linear equalizers selectively included in the clock path defines delay through the clock path.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, further comprising a multiplexer in the clock path to select an output of one of the linear equalizers.

### Claim 11

A sequential logic system comprising:
a sequential storage element to capture a data signal on edges of a clock signal;
a data path to communicate the data signal to the sequential storage element;
a clock path to communicate the clock signal to the sequential storage element, the clock path including an equalizer to suppress high-frequency components relative to low-frequency components of the clock signal; and
feedback circuitry between an output of the sequential storage element and the equalizer, the feedback circuitry to adjust the equalizer responsive to the captured data signal.

### Claim 12 (depends on 11)

The sequential logic system of claim 11, wherein the equalizer is a continuous-time equalizer.

### Claim 13 (depends on 11)

The sequential logic system of claim 11, wherein the equalizer is a linear equalizer.

### Claim 14 (depends on 11)

The sequential logic system of claim 11, further comprising an integrated circuit device having a clock source coupled to the clock path to deliver the clock signal and a data driver coupled to the data path to deliver the data signal.

### Claim 15 (depends on 14)

The sequential logic system of claim 14, wherein the integrated circuit further comprises a second equalizer in the data path.

### Claim 16 (depends on 11)

The sequential logic system of claim 11, wherein the sequential storage element is instantiated on a second integrated circuit device.

### Claim 17 (depends on 16)

The sequential logic system of claim 16, wherein the second integrated circuit device further includes a second equalizer in the data path.

### Claim 18 (depends on 17)

The sequential logic system of claim 17, wherein the first-mentioned equalizer is instantiated on the second integrated circuit device.

### Claim 19 (depends on 17)

The sequential logic system of claim 17, wherein the first-mentioned and second equalizers are continuous-time, linear equalizers.

### Claim 20 (depends on 11)

The sequential logic system of claim 11, wherein the edges of the clock signal include a first edge and subsequent edges, and wherein the feedback circuitry adjusts the equalizer based on the phase of the first edge relative to the phases of the subsequent edges.

### Claim 21

A method of timing receipt of a data signal, the method comprising:
timing the data signal to a clock signal using a first sequential storage element;
equalizing the clock signal, using an equalizer, to emphasize lower-frequency components of the clock signal relative to higher-frequency components of the clock signal;
transmitting the data and the equalized clock signal to a second sequential storage element;
sampling the data signal, using the second sequential storage element, on edges of the equalized clock signal; and
adjusting the equalizing responsive to errors in the sampled data signal.

### Claim 22 (depends on 21)

The method of claim 21, further comprising equalizing the data signal, using a second equalizer, before sampling the data signal.

### Claim 23 (depends on 21)

The method of claim 21, wherein the equalizer is a linear equalizer.

### Claim 24 (depends on 23)

The method of claim 23, wherein the equalizer is a continuous-time equalizer.

### Claim 25 (depends on 23)

The method of claim 23, wherein transmitting the equalized clock signal comprises amplifying the equalized clock signal using a linear amplifier.

### Claim 26

A communication system comprising:
a data path to convey a data signal expressed as a series of symbols following a null period, the series of symbols including an initial symbol followed by subsequent symbols;
a clock path having an equalizer to convey an equalized clock signal expressed as a series of clock edges following the null period, the clock edges including an initial clock edge followed by subsequent clock edges; and
a data sampler having a data input node to receive the initial and subsequent symbols and a clock node to receive the initial and subsequent clock edges, the data sampler to sample the initial symbol using the initial clock edge.

### Claim 27 (depends on 26)

The communication system of claim 26, wherein the equalizer is a linear equalizer.

### Claim 28 (depends on 26)

The communication system of claim 26, wherein the equalizer is a continuous-time equalizer.

### Claim 29 (depends on 26)

The communication system of claim 26, wherein the clock path further includes a clock buffer.

### Claim 30 (depends on 26)

The communication system of claim 26, further comprising feedback circuitry coupled to the equalizer to adjust the phase of the initial clock edge relative to the phases of the subsequent clock edges.