# US 2014/0152356 A1 · Frequency tracing circuit and method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152356 A1 - Document ID: US20140152356A1 - Status: Published application - Kind: A1 - Application number: 13/803,476 - Filed: 2013-03-14 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: National Taiwan University - Applicants: National Taiwan University - Inventors: TSUNG-HSIEN LIN; CHENG-EN LIU; CHEN-CHIEN LIN; WEI-HAO CHIU; SUNG-LIN TSAI - Web page: https://patentgrep.com/patent/US20140152356A1 ## CPC - H04L 7/0331: {with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock (H04L7/0337 takes precedence)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal. ## Claims ### Claim 1 A frequency tracking circuit for a clock and data recovery circuit, the frequency tracking circuit comprising: an edge selector, receiving a data signal and a feedback clock signal and sequentially outputting a data edge signal and a feedback-clock-edge signal; a phase-frequency processor, receiving the data edge signal and the feedback-clock-edge signal, and outputting a frequency adjusting digital signal after executing a differential operation according to a first phase difference and a second phase difference; and a digital controlled oscillator, connected to the phase-frequency processor, and the digital controlled oscillator receiving the frequency adjusting digital signal so as to adjust a frequency of the feedback clock signal, wherein the phase-frequency processor outputs a frequency tracking signal to the edge selector, and the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal. ### Claim 2 (depends on 1) The frequency tracking circuit according to claim 1, wherein a first phase difference is a phase difference between a previous data edge signal and a previous feedback-clock-edge signal, and a second phase difference is a phase difference between the data edge signal and the feedback-clock-edge signal. ### Claim 3 (depends on 1) The frequency tracking circuit according to claim 1, wherein a phase of the data edge signal leads a phase of the feedback-clock-edge signal. ### Claim 4 (depends on 1) The frequency tracking circuit according to claim 1, wherein the phase-frequency processor comprising: a time-digital converter, connected to the edge selector, and the time-digital converter converts a phase difference between the data edge signal and the feedback-clock-edge signal into a phase difference digital signal; a digital differentiator, receiving the phase difference digital signal, and the digital differentiator executing a digital difference operation on a digital signal having a second phase difference between the data edge signal and the feedback-clock-edge signal and a digital signal having a first phase difference between a previous data edge signal and a previous feedback-clock-edge signal, and correspondingly outputting a frequency information digital signal a comparator, connected to the digital differentiator, and the comparator executes a comparison operation according to the frequency information digital signal received, wherein when a result of the comparison operation executed by the comparator is larger than zero, the comparator outputs a frequency counting digital signal with a frequency-up command; when the result of the comparison operation is smaller than zero, the comparator outputs the frequency counting digital signal with a frequency-down command; and a counter, receiving the frequency counting digital signal and accordingly counting and outputting a frequency adjusting digital signal, wherein the edge selector, the digital differentiator, the comparator, and the counter further receive a frequency tracking signal. ### Claim 5 (depends on 1) The frequency tracking circuit according to claim 1, wherein when the frequency tracking signal is a high level voltage, and the edge selector, the digital differentiator, the comparator, and the counter execute a frequency tracing work, and after the frequency tracking signal experiencing enabling duration of high level voltage twice in a row, the digital controlled oscillator adjusts the frequency of the feedback clock signal. ### Claim 6 (depends on 1) The frequency tracking circuit according to claim 1, wherein the edge selector comprising: a first D-type flip-flop, having a data input end receiving a frequency tracking signal, a clock input end receiving a data signal, and an output end outputting a data edge signal; and a second D-type flip-flop, having a data input end receiving the data edge signal, a clock input end receiving a feedback clock signal, an output end outputting a feedback-clock-edge signal. ### Claim 7 (depends on 4) The frequency tracking circuit according to claim 4, wherein the time-digital converter comprising: M first delay units, connected to each other in series, wherein each has a first delay time, and the Xth of the M first delay units receives the feedback-clock-edge signal which has been delayed for X−1 times of the first delay time, and outputs the feedback-clock-edge signal which has been delayed for X times of the first delay time, wherein X is positive integer between 1 to M; M second delay units, connected to each other in series, wherein each has a second delay time, and the Yth of the M second delay units receives the data edge signal which has been delayed for Y−1 times of the second delay time, and outputting the data edge signal which has been delayed for Y times of the second delay time, wherein Y is positive integer between 1 to M; a NAND gate, receiving the feedback-clock-edge signal which has been delayed for M times of the first delay time and the data edge signal which has been delayed for M times of the second delay time, and outputs the frequency tracking signal; M time amplifiers, wherein the Zth of the plurality of the M time amplifiers is correspondingly connected to an output end of the Zth of the plurality of the M first delay units and an output end of the Zth of the plurality of the M second delay units, and the time amplifiers amplify the phase difference between the data edge signal delayed and the feedback-clock-edge signal delayed, and output a phase leading digital signal, wherein Z is positive integer between 1 to M; M of third D-type flip-flops, and each clock input end of the M of the third D-type flip-flops receives the frequency tracking signal NEXT, and the Wth of the third D-type flip-flops receives the phase leading digital signal of the Wth of the time amplifiers, wherein W is positive integer between 1 to M; and an encoder, connected the third D-type lip-flops, and the encoder receiving the phase leading digital signal transmitted by the M D-type flip-flops, and proceeds a coding to form a phase difference digital signal, wherein the second delay time is longer than the first delay time, and M is an integer. ### Claim 8 (depends on 7) The frequency tracking circuit according to claim 7, wherein the plurality of the third D-type flip-flop and the encoder further receive the frequency tracking signal. ### Claim 9 (depends on 7) The frequency tracking circuit according to claim 7, wherein when the phase of the data edge signal leads the phase of the feedback-clock-edge signal, then a digital logic of the phase leading digital signal is “one”; when the phase of the data edge signal is lags the phase of the feedback-clock-edge signal, then the digital logic of the phase leading digital signal is “zero.” ### Claim 10 (depends on 4) The frequency tracking circuit according to claim 4, wherein the digital differentiator comprising: a fourth D-type flip-flop, having a data input end receiving the phase difference digital signal, and a clock input end of the D-type flip-flop receives the frequency tracking signal; and a digital operator, connected to the data input end of the fourth D-type flip-flop and a data output end, wherein the digital operator takes the phase difference digital signal minus a previous phase difference digital signal, and outputs a frequency information digital signal. ### Claim 11 A frequency tracking method for a clock and data recovery circuit, and the clock and data recovery circuit includes a frequency tracking circuit, and the frequency tracking circuit includes an edge selector, a phase-frequency processor, a digital controlled oscillator, wherein the phase-frequency processor is connected to the edge selector, and the digital controlled oscillator is connected to the edge selector, and the frequency tracking method includes: receiving a data signal and a feedback clock signal, and sequentially outputting a data edge signal and a feedback-clock-edge signal; receiving the data edge signal and the feedback-clock-edge signal; outputting a frequency adjusting digital signal after a differential operation according to a first phase difference second phase difference; and adjusting a frequency of the feedback clock signal outputted according to the frequency adjusting digital signal, wherein a phase-frequency processor outputs a frequency tracking signal to an edge selector, and the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal. ### Claim 12 (depends on 11) The frequency tracking method according to claim 11, wherein a phase of the data edge signal leads a phase of the feedback-clock-edge signal. ### Claim 13 (depends on 11) The frequency tracking method according to claim 11, wherein the phase-frequency processor comprising: a time-digital converter, connected to the edge selector, and the time-digital converter converts a phase difference between the data edge signal and the feedback-clock-edge signal into a phase difference digital signal; a digital differentiator, receiving the phase difference digital signal, and the digital differentiator executing a digital difference operation on a digital signal having a second phase difference between the data edge signal and the feedback-clock-edge signal and a digital signal having a first phase difference between a previous data edge signal and a previous feedback-clock-edge signal, and correspondingly outputting a frequency information digital signal a comparator, connected to the digital differentiator, and the comparator executing a comparison operation according to the frequency information digital signal received, wherein when a result of the comparison operation executed by the comparator is larger than zero, the comparator outputs a frequency counting digital signal with a frequency-up command; when the result of the comparison operation is smaller than zero, the comparator outputs the frequency counting digital signal with a frequency-down command, and; a counter, receiving the frequency counting digital signal and accordingly counting and outputting a frequency adjusting digital signal, wherein the edge selector, the digital differentiator, the comparator, and the counter further receive a frequency tracking signal. ### Claim 14 (depends on 13) The frequency tracking method according to claim 13, wherein when the frequency tracking signal is a high level voltage, and the edge selector, the digital differentiator, the comparator, and the counter execute a frequency tracing work, and after the frequency tracking signal experiences high level voltage of enabling duration twice in a row, the digital controlled oscillator adjusts the frequency of the feedback clock signal. ### Claim 15 (depends on 11) The frequency tracking method according to claim 11, wherein the edge selector comprising: a first D-type flip-flop, having a data input end receiving a frequency tracking signal, a clock input end receiving a data signal, and an output end outputting a data edge signal; and a second D-type flip-flop, having a data input end receiving the data edge signal, a clock input end receiving a feedback clock signal, and an output end outputting a feedback-clock-edge signal. ### Claim 16 (depends on 13) The frequency tracking method according to claim 13, wherein the time-digital converter comprising: M first delay units, connected to each other in series, wherein each has a first delay time, and the Xth of the M first delay units receives the feedback-clock-edge signal which has been delayed for X−1 times of the first delay time, and outputting the feedback-clock-edge signal which has been delayed for X times of the first delay time, wherein X is positive integer between 1 to M; M second delay units, connected to each other in series, wherein each has a second delay time, and the Yth of the M second delay units receives the data edge signal which has been delayed for Y−1 times of the second delay time, and outputting the data edge signal which has been delayed for M times of the second delay time, wherein Y is positive integer between 1 to M; a NAND gate, receiving the feedback-clock-edge signal which has been delayed for M times of the first delay time and the data edge signal which has been delayed for M times of the second delay time, and outputs the frequency tracking signal; M time amplifiers, wherein the Zth of the plurality of the M time amplifiers is correspondingly connected to an output end of the Zth of the plurality of the M first delay units and an output end of the Zth of the plurality of the M second delay units, and the time amplifiers amplify the phase difference between the data edge signal delayed and the feedback-clock-edge signal delayed, and output a phase leading digital signal, wherein Z is positive integer between 1 to M; M of third D-type flip-flops, and each clock input end of the M of the third D-type flip-flops receives the frequency tracking signal NEXT, and the Wth of the third D-type flip-flops receives the phase leading digital signal of the Wth of the time amplifiers, wherein W is positive integer between 1 to M; and an encoder, connected the third D-type flip-flops, and the encoder receiving the phase leading digital signal transmitted by the M D-type flip-flops, and proceeds a coding to form a phase difference digital signal, wherein the second delay time is longer than the first delay time, and M is an integer. ### Claim 17 (depends on 16) The frequency tracking method according to claim 16, wherein the plurality of the third D-type flip-flop and the encoder further receive the frequency tracking signal. ### Claim 18 (depends on 16) The frequency tracking method according to claim 16, wherein when the phase of the data edge signal leads the phase of the feedback-clock-edge signal, then a digital logic of the phase leading digital signal is “one”; when the phase of the data edge signal lags the phase of the feedback-clock-edge signal, then the digital logic of the phase leading digital signal is “zero.” ### Claim 19 (depends on 13) The frequency tracking method according to claim 13, wherein the digital differentiator comprising: a fourth D-type flip-flop, having a data input end receiving the phase difference digital signal, and a clock input end receiving the frequency tracking signal; and a digital operator, connected to the data input end of the fourth D-type flip-flop and a data output end, wherein the digital operator takes the phase difference digital signal minus a previous phase difference digital signal, and outputting a frequency information digital signal. ### Claim 20 (depends on 11) The frequency tracking method according to claim 11, wherein a first phase difference is a phase difference between a previous data edge signal and a previous feedback-clock-edge signal, and a second phase difference is a phase difference between the data edge signal and the feedback-clock-edge signal.