# US 2014/0152349 A1 · Semiconductor device, manufacturing method thereof and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152349 A1 - Document ID: US20140152349A1 - Status: Published application - Kind: A1 - Application number: 13/690,597 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Macronix International Co., Ltd. - Applicants: Macronix International Co., Ltd. - Inventors: Chih-Ling Hung; Hsin-Liang Chen; Wing-Chor Chan - Web page: https://patentgrep.com/patent/US20140152349A1 ## CPC - H03K 17/063: {in field-effect transistor switches} - H10D 89/711: {using bipolar transistors as protective elements} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device, a manufacturing method thereof and an operating method thereof are provided. The semiconductor device includes a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer. The first and the second wells are disposed on the substrate. The first and the third heavily doping regions, which are separated from each other, are disposed in the first well, and the second heavily doping region is disposed in the second well. The electrode layer is disposed on the first well. Each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping. Each of the substrate, the first well, and the third heavily doping region has a second type doping, which is complementary to the first type doping. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a first well disposed on the substrate; a second well disposed on the substrate; a first heavily doping region disposed in the first well; a second heavily doping region disposed in the second well; a third heavily doping region disposed in the first well, wherein the first heavily doping region and the third heavily doping region are separated from each other; and an electrode layer disposed on the first well; wherein each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping, each of the substrate, the first well, and the third heavily doping region has a second type doping, and the first type doping is complementary to the second type doping. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a field oxide (FOX) disposed on a junction between the first well and the second well. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising: a buried layer disposed below the first well and the second well, wherein the buried layer has the first type doping. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, further comprising: a third well disposed on the substrate, wherein the first well is disposed between the second well and the third well, and the third well has the first type doping. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the electrode layer is disposed on the third well. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the first well comprises a first region and a second region, the first heavily doping region is in the first region, the third heavily doping region is in the second region, and a partial region of the third well is located between the first region and the substrate. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, further comprising: a buried layer disposed below the first well, the second well, and the third well, wherein the buried layer has the first type doping. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second well surrounds the first well. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the electrode layer is disposed on the second well. ### Claim 10 A manufacturing method of a semiconductor device, comprising: providing a substrate; forming a first well and a second well on the substrate; forming a first heavily doping region in the first well; forming a second heavily doping region in the second well; forming a third heavily doping region in the first well, wherein the first heavily doping region and the third heavily doping region are separated from each other; and forming an electrode layer on the first well, wherein each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping, each of the substrate, the first well, and the third heavily doping region has a second type doping, and the first type doping is complementary to the second type doping. ### Claim 11 (depends on 10) The manufacturing method of the semiconductor device according to claim 10, further comprising: forming a filed oxide (FOX) on a junction between the first well and the second well. ### Claim 12 (depends on 10) The manufacturing method of the semiconductor device according to claim 10, further comprising: forming a buried layer below the first well and the second well, wherein the buried layer has the first type doping. ### Claim 13 (depends on 10) The manufacturing method of the semiconductor device according to claim 10, further comprising: forming a third well on the substrate, wherein the first well is located between the second well and the third well, and the third well has the first type doping. ### Claim 14 (depends on 13) The manufacturing method of the semiconductor device according to claim 13, wherein the electrode layer is disposed on the third well. ### Claim 15 (depends on 13) The manufacturing method of the semiconductor device according to claim 13, wherein the step of forming the first step comprises: forming a first region and a second region, wherein the first heavily doping region is in the first region, the third heavily doping region is in the second region, and a partial region of the third well is located between the first region and the substrate. ### Claim 16 (depends on 15) The manufacturing method of the semiconductor device according to claim 15, further comprising: forming a buried layer below the first well, the second well, and the third well, wherein the buried layer has the first type doping. ### Claim 17 (depends on 10) The manufacturing method of the semiconductor device according to claim 10, wherein the second well surrounds the first well. ### Claim 18 (depends on 17) The manufacturing method of the semiconductor device according to claim 17, wherein the electrode layer is formed on the second well. ### Claim 19 An operating method of a semiconductor device, wherein the semiconductor device comprises a substrate, a first well, a second well, a first heavily doping region, a second heavily doping region, a third heavily doping region, and an electrode layer; the first well and second well are disposed on the substrate; the first heavily doping region is disposed in the first well; the second heavily doping region is disposed in the second well; the third well is disposed in the first well and is separated from the first well; the electrode layer is disposed on the first well; each of the second well, the first heavily doping region, and the second heavily doping region has a first type doping; each of the substrate, the first well, and the third heavily doping region has a second type doping; the first type doping is complementary to the second type doping; and the operating method comprises: applying a gate voltage to the electrode layer for generating an inversion layer between the first well and the electrode layer; applying an emitter voltage to the first heavily doping region; applying a collector voltage to the second heavily doping region; and applying a base voltage to the third heavily doping region. ### Claim 20 (depends on 19) The operating method of the semiconductor device according to claim 19, wherein the gate voltage is between larger than 0 and smaller than 1 V.