# US 2014/0152347 A1 · Variable phase shifter, semiconductor integrated circuit and phase shifting method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152347 A1 - Document ID: US20140152347A1 - Status: Published application - Kind: A1 - Application number: 14/029,040 - Filed: 2013-09-17 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: MASARU SATO - Web page: https://patentgrep.com/patent/US20140152347A1 ## CPC - H03B 21/00: Generation of oscillations by combining unmodulated signals of different frequencies (H03B19/00 takes precedence; frequency changing circuits in general H03D) - H03H 11/20: Two-port phase shifters providing an adjustable phase shift - H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H) - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) ## Abstract A variable phase shifter. The variable phase shifter includes: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer. ## Claims ### Claim 1 A variable phase shifter comprising: a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency; a synthesizer that includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports so that parasitic capacitance becomes load impedance for the transmission line, and that on input of the input signal takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer. ### Claim 2 (depends on 1) The variable phase shifter of claim 1, wherein the phase controller controls bias voltages respectively applied to gates of each of the first and second transistors connected to the pair of output ports based on a target phase of the output signal. ### Claim 3 (depends on 2) The variable phase shifter of claim 2, wherein the phase controller includes: a power source section that outputs a stepwise set voltage; and a voltage controller that controls the power source section so as to output as a bias voltage a voltage set based on the target phase from out of the stepwise set voltages. ### Claim 4 (depends on 3) The variable phase shifter of claim 3, wherein when from out of the stepwise set voltages a third voltage between the first voltage and the second voltage is output from the power source section as the bias voltage, the phase controller controls the output time of the first voltage and the output time of the second voltage base on the first, second and third voltages. ### Claim 5 (depends on 2) The variable phase shifter of claim 2, further comprising: an electrostatic capacitance element of specific electrostatic capacitance connected to the first or the second port of the pair of output ports so as to configure the load impedance; and a switch member that switches the load impedance by disconnecting and connecting the electrostatic capacitance element from the output port to which the electrostatic capacitance element was connected, wherein the phase controller controls to switch the load impedance using the switch member based on the target phase. ### Claim 6 (depends on 5) The variable phase shifter of claim 5, wherein the switch member is a third transistor, and electrostatic capacitance of the electrostatic capacitance element is parasitic capacitance of the third transistor. ### Claim 7 (depends on 2) The variable phase shifter claim 2, further comprising: a third transistor that is connected to the first or second port of the pair of output ports, and whose parasitic capacitance is added as the load impedance by ON operation of the third transistor, wherein the phase controller controls switching operation of the third transistor based on the target phase. ### Claim 8 A semiconductor integrated circuit comprising: a variable phase shifter that includes: a synthesizer that, for a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency, includes a first transistor connected to a first port of the pair of output ports and a second transistor connected to a second port of the pair of output ports so that parasitic capacitance becomes load impedance for the transmission line, and that on input of the input signal to the transmission line takes signals output from the pair of output ports of the transmission line with a phase according to their respective load impedances and employs the first and the second transistors to amplify and combine the signals; and a phase controller that controls the phase of the output signal that is combined and output by the synthesizer by controlling the amplification operation of each of the first and second transistors of the synthesizer. ### Claim 9 (depends on 8) The semiconductor integrated circuit of claim 8, further comprising: the transmission line. ### Claim 10 (depends on 8) The semiconductor integrated circuit of claim 8, wherein the phase controller includes: a power source section that outputs a stepwise set voltage; and a voltage controller that controls the power source section so as to output as respective bias voltages to the first and second transistors a voltage set for the target phase from out of the stepwise set voltages. ### Claim 11 (depends on 10) The semiconductor integrated circuit of claim 10, further comprising: an electrostatic capacitance element of specific electrostatic capacitance connected to the first or the second port of the pair of output ports so as to configure the load impedance; and a switch member that switches the load impedance by disconnecting and connecting the electrostatic capacitance element from the output port to which the electrostatic capacitance element was connected, wherein the phase controller controls to switch the load impedance using the switch member based on the target phase. ### Claim 12 (depends on 11) The semiconductor integrated circuit of claim 11, wherein the switch member is a third transistor, and electrostatic capacitance of the electrostatic capacitance element is parasitic capacitance of the third transistor. ### Claim 13 (depends on 10) The semiconductor integrated circuit of claim 10, further comprising: a third transistor that is connected to the first or second port of the pair of output ports, and whose parasitic capacitance is added as the load impedance by ON operation of the third transistor, wherein the phase controller controls switching operation of the third transistor based on the target phase. ### Claim 14 A phase shifting method comprising: for a transmission line that outputs quadrature signals from a pair of output ports in response to an input signal of a specific frequency, connecting a first transistor to a first port of the pair of output ports so that parasitic capacitance becomes load impedance for the transmission line; connecting a second transistor (Mb) to a second port of the pair of output ports so that parasitic capacitance becomes load impedance for the transmission line; and when employing the first and the second transistors to amplify and combine signals that on input of the input signal to the transmission line are output from the pair of output ports with a phase according to their respective load impedances, controlling the phase of the combined output signal by controlling the amplification operation of each of the first and second transistors. ### Claim 15 (depends on 14) The phase shifting method of claim 14, wherein the phase and amplitude of the output signal is controlled by controlling respective bias voltages applied to gates of the first and second transistors connected to the pair of ports. ### Claim 16 (depends on 14) The phase shifting method of claim 14, further comprising: connecting an electrostatic capacitance element of specific electrostatic capacitance to the first or the second port of the pair of output ports; connecting a switch member so as to disconnect and connect the electrostatic capacitance element from the output port to which the electrostatic capacitance element was connected; and switching the load impedance using the switch member based on a target phase. ### Claim 17 (depends on 16) The phase shifting method of claim 16, wherein a third transistor is employed as the switch member so that parasitic capacitance configures electrostatic capacitance of the electrostatic capacitance element. ### Claim 18 (depends on 14) The phase shifting method of claim 14, further comprising: connecting a third transistor to the first or second port of the pair of output ports so that parasitic capacitance is added as the load impedance by ON operation of the third transistor; and controlling switching operation of the third transistor based on the target phase.