# US 2014/0152345 A1 · Sense-amplifier latch having single data input > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152345 A1 - Document ID: US20140152345A1 - Status: Published application - Kind: A1 - Application number: 13/690,080 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: LSI Corporation - Applicants: Lsi Corporation - Inventors: Manish Trivedi; Manish Umedlal Patel - Web page: https://patentgrep.com/patent/US20140152345A1 ## CPC - H03K 5/153: Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant (switching at zero crossing H03K17/13) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract A latch circuit comprises true and complement data nodes. During a setup period of a latching operation, true node setup circuitry draws the true data node toward an input data signal in parallel with complement node setup circuitry drawing the complement node upward toward a high-voltage reference source (VDD) when the data signal is low or downward toward a low-voltage reference source (VSS) when the data signal is high. After the setup period, true and complement clock signals are used as control signals to turn the setup circuitry off and amplification circuitry on. The amplification circuitry, which comprises a pair of cross-coupled inverters coupled between VDD and VSS, is capable of resolving relatively small voltage differentials between the true and complement nodes by pulling the true node (i) upward toward VDD when the data signal is high and (ii) downward toward VSS when the data signal is low. ## Claims ### Claim 1 An apparatus comprising a latch circuit (e.g., 100, 300, 400, 500) comprising: a true node (e.g., DT); a complement node (e.g., DC); true node setup circuitry (e.g., 102, 302, 402, 504) configured to selectively connect the true node to an input data value; complement node setup circuitry (e.g., 104, 304, 404, 502) configured to selectively connect the complement node to either a high-voltage reference source or a low-voltage reference source; and amplification circuitry (e.g., 106, 306, 406, 506) coupled to the true node and the complement node, wherein the amplification circuitry is configured to amplify a voltage differential between the true node and the complement node. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the complement node setup circuitry (e.g., 104, 304) comprises: a first switch (e.g., 130) configured to selectively connect the complement node to the high-voltage reference source based on the input data value; and a second switch (e.g., 128) configured to selectively connect the complement node to the low-voltage reference source based on the input data value. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the complement node setup circuitry (e.g., 404, 502) comprises at least one switch configured to selectively connect the complement node to the high-voltage reference source based on a clock signal. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the amplification circuitry comprises a pair of cross-coupled inverters (e.g., 108/110, 408/410) coupled to the true node and the complement node. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the amplification circuitry further comprises: a first switch (e.g., 112) configured to selectively connect the cross-coupled inverters to the high-voltage reference source; and a second switch (e.g., 114) configured to selectively connect the cross-coupled inverters to the low-voltage reference source. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein: the cross-coupled inverters (408/410) are configured in an unbalanced configuration; the cross-coupled inverters are fixedly connected to the high-voltage reference source; and the amplification circuitry comprises a first switch (e.g., 414) configured to selectively connect the cross-coupled inverters to the low-voltage reference source. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein: the complement node setup circuitry (e.g., 104, 304) comprises: a first switch (e.g., 130) configured to selectively connect the complement node to the high-voltage reference source based on the input data value; and a second switch (e.g., 128) configured to selectively connect the complement node to the low-voltage reference source based on the input data value; and the amplification circuitry comprises: a pair of cross-coupled inverters (e.g., 108/110) coupled to the true node and the complement node; a first switch (e.g., 112) configured to selectively connect the cross-coupled inverters to the high-voltage reference source; and a second switch (e.g., 114) configured to selectively connect the cross-coupled inverters to the low-voltage reference source. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein: the complement node setup circuitry (e.g., 404, 502) comprises at least one switch configured to selectively connect the complement node to the high-voltage reference source based on a clock signal; and the amplification circuitry comprises: a pair of cross-coupled inverters (e.g., 408/410) coupled to the true node and the complement node, wherein: the cross-coupled inverters are configured in an unbalanced configuration; and the cross-coupled inverters are fixedly connected to the high-voltage reference source; and a first switch (e.g., 414) configured to selectively connect the cross-coupled inverters to the low-voltage reference source. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the latch circuit is configured to receive true and complement clock signals (e.g., CK, CKB) used to control operations of one or more of the true node setup circuitry, the complement node setup circuitry, and the amplification circuitry. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the apparatus further comprises clock generation circuitry configured to receive a reference clock signal and generate the true and complement clock signals. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the clock generation circuitry comprises: an inverter (e.g., 702, 902) configured to (i) operate between a high-voltage reference source (e.g., VDD), and a low-voltage reference source (e.g., VSS), (ii) receive a reference clock signal, and (iii) generate a complement reference clock signal being the complement of the reference clock signal; true signal generation circuitry (e.g., 704, 904) configured to (i) operate between (a) one of the high-voltage reference source and the low-voltage reference source and (b) one of the true input signal and the complement input signal and (ii) generate a true output signal (e.g., OUT); and complement signal generation circuitry (e.g., 706, 906) configured to (i) operate between (a) one of the high-voltage reference source and the low-voltage reference source and (b) one of the true input signal and the complement input signal and (ii) generate a complement output signal (e.g., OUTB). ### Claim 12 The apparatus of claim of 11, wherein skew between the true and complement output signals is less than skew between the reference clock and complement reference clock signals. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the apparatus is an integrated circuit. ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the apparatus is a memory circuit. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein a setup and hold period of the latch circuit is less than or equal to one gate delay. ### Claim 16 A method for latching an input data value in a latch circuit, the method comprising: (a) selectively connecting a true node of the latch circuit to the input data value; (b) selectively connecting a complement node to either a high-voltage reference source or a low-voltage reference source based on the input data value; and (c) amplifying a voltage differential between the true node and the complement node. ### Claim 17 (depends on 16) The method of claim 16, wherein step (b) comprises: (b1) selectively connecting the complement node to the high-voltage reference source when the input data value is low; and (b2) selectively connecting the complement node to the low-voltage reference source when the input data value is high. ### Claim 18 (depends on 16) The method of claim 16, wherein step (b) comprises selectively connecting the complement node to the high-voltage reference source when the input data value is high and when the input data value is low.