# US 2014/0152343 A1 · Super cmos devices on a microelectronics system

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- Number: US 2014/0152343 A1
- Document ID: US20140152343A1
- Status: Published application
- Kind: A1
- Application number: 13/931,315
- Filed: 2013-06-28
- Published: 2014-06-05
- Earliest claimed: 2008-12-23
- Assignees: Schottky Lsi, Inc.
- Applicants: Schottky LSI, Inc.
- Inventors: AUGUSTINE WEI-CHUN CHANG
- Web page: https://patentgrep.com/patent/US20140152343A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H10B 12/50: {Peripheral circuit region structures}
- H10B 20/00: Read-only memory [ROM] devices
- H10B 20/38: {Doping programmed, e.g. mask ROM}
- H10B 20/60: {Peripheral circuit regions}
- H10B 20/65: {of memory structures of the ROM only type}
- H10B 41/40: characterised by the peripheral circuit region
- H10B 41/49: comprising different types of peripheral transistor
- H10D 8/051: {of Schottky diodes}
- H10D 8/60: Schottky-barrier diodes
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/907: {CMOS gate arrays}
- H10D 89/10: Integrated device layouts
- H10F 10/16: Photovoltaic cells having only PN heterojunction potential barriers
- H10F 10/164: comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
- H10F 10/18: Photovoltaic cells having only Schottky potential barriers
- H10F 77/12: Active materials
- H10F 77/166: Amorphous semiconductors
- H10F 77/1662: {including only Group IV materials}
- H10W 90/00: Package configurations
- H10D 1/47: Resistors having no potential barriers
- Y02E 10/50: Photovoltaic [PV] energy
- Y02E 10/548: Amorphous silicon PV cells
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION

## Abstract

A low cost IC solution is disclosed in accordance with an embodiment to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros are composed of diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

## Claims

### Claim 1

A subsystem comprising:
a substrate; and
a plurality of devices placed on the substrate; wherein the plurality of integrated circuits are formed with a plurality of programming, resources, logic memory and timing control micro functions.

### Claim 2 (depends on 1)

The subsystem of claim 1 wherein the devices comprise a plurality of fixed threshold and variable threshold complementary transistors, complementary Schottky low barrier diodes, poly silicon film resistors, capacitors and wiring tracks are placed wherein integrated circuits are formed with a plurality of programming, resources, logic memory and timing control macro functions.

### Claim 3 (depends on 2)

The subsystem of claim 2, which includes device isolation by oxide filled trenches, binary threshold and multi-level threshold transistors, to provide low and high barrier Schottky diodes.

### Claim 4 (depends on 2)

The subsystem of claim 2 wherein programming resources are provided to adjust the threshold of the distributed individual and large banks of the variable threshold transistors.

### Claim 5 (depends on 2)

The subsystem of claim 2 wherein programming means and resources are provided to form certain re-configurable logic gate array circuit units.

### Claim 6 (depends on 2)

The subsystem of claim 2 wherein programming means and resources are provided and to complete certain network connections among various functional units in the chip.

### Claim 7 (depends on 2)

The subsystem of claim 2 wherein programming means and resources may include state tables, virtual machines, setup or initialization and test procedures, data access, transport, and storage algorithms, protocols.

### Claim 8 (depends on 2)

The subsystem of claim 2 wherein the hardware constructs in claim 2 are comprised of hardwired Schottky CMOS Logic (SCL) gate array and memory units, timing or phase detector, audio, video, and text signal detector, rectifier and decoder, mixer, multiplexer, signal filter and separator, charge pump, delay element, phase splitter, frequency synthesizer, phase locker, and D-type register, wherein these circuits are intrinsically faster but easier to control, operated with lower supply voltage, and have less sensitivity to body-effects.

### Claim 9 (depends on 7, 8)

The subsystem of claim 8 wherein the phase detector is configured from simple SCL type NAND gates, which replace conventional CMOS-TTL gates having less than 2-way logic or serial gating, wherein the charge-pump output of claim 7 directly couples to the current source of the delay element with a positive feedback in stage delays.

### Claim 10 (depends on 8)

The subsystem of claim 8 wherein the delay element chain forms a voltage-controlled oscillator via a programmable mux and its selected long or short loop paths, wherein one can form a 12 MHz low frequency oscillator, which can be stabilized by an off-chip Resistor-crystal tank control at chip/PCB boundaries.

### Claim 11 (depends on 8)

The subsystem of claim 8 wherein the delay element may form on-chip free running internal oscillator with extremely high frequency up to several GHz, wherein it was then divided to mid or lower frequency (10s-100s MHz) by conventional D-type flip-flop means for monitoring and control.

### Claim 12 (depends on 8)

The subsystem of claim 8 wherein the phase splitter can subdivide the low frequency delay period therefore placing the switching edge of the low frequency oscillator waveform accurately with controlled spacing, wherein two frequency synthesis means (FIGS. 3E and 6A) are proposed to form ultra high frequency pulses (several GHz) by combining the delayed edges with SCL type NOR gates.

### Claim 13 (depends on 7, 8)

The subsystem of claim 8 wherein a SCL type double ring phase coupler forms a phase lock of claim 7 for non-overlapped clocks, which is then fan-out expanded by inverter chains.

### Claim 14 (depends on 2)

The subsystem of claim 2 wherein the hardware constructs are comprised of software driven SCL gate arrays, IO transceivers, terminators, capacitors, and wherein the switching transistor is of the variable threshold type.

### Claim 15 (depends on 1)

The subsystem of claim 1 wherein the hardware constructs are comprised of software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switching transistor is of the fixed threshold type.

### Claim 16 (depends on 1)

The subsystem of claim 1 wherein the hardware constructs are comprised of software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switching transistor is of the variable threshold type, and the SCL unit act as analog signal comparator.

### Claim 17 (depends on 1)

The subsystem of claim 1 wherein the analog comparator construct includes a pass transistor construct for sampling reference voltages.

### Claim 18 (depends on 1)

The subsystem of claim 1 wherein the hardware constructs are comprised of software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switching transistor is of the variable threshold type, and the switching transistor may store multiple bits with other dedicated apparatus and software links.

### Claim 19 (depends on 1)

The subsystem of claim 1 wherein the dedicated apparatus consists of input status registers, charge pump circuitry, and stored software means in the local memory arrays.

### Claim 20 (depends on 1)

The subsystem of claim 1 wherein the hardware construct are comprised of software driven SCL gate arrays, IO transceivers, terminators, capacitors, wherein the switch transistor is of the variable threshold type, and the SCL unit may process multi-value logic operations with binary, ternary and quaternary operators.