# US 2014/0152342 A1 · Cmos differential logic circuit using voltage boosting technique > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152342 A1 - Document ID: US20140152342A1 - Status: Published application - Kind: A1 - Application number: 13/770,546 - Filed: 2013-02-19 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Research & Business Foundation Sungkyunkwan University - Inventors: Bai Sun KONG; Jong Woo KIM; Joo Seong KIM - Web page: https://patentgrep.com/patent/US20140152342A1 ## CPC - H03K 19/018528: {with at least one differential stage} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present invention discloses a CMOS differential logic circuit. The CMOS differential logic circuit includes a precharge differential logic unit, which is precharged to a source voltage in response to a clock signal and is configured to output voltage having an increased load-driving ability using a boosting voltage; a voltage-boosting unit, which is pulled down by a ground voltage in response to the clock signal and is configured to boost the pulled-down voltage using capacitive coupling and output the boosting voltage; and a switching unit, which is configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. The propagation delay of a signal from the input terminal to the output terminal of a circuit in a low-source-voltage environment can be reduced, and the operating speed of the circuit and energy efficiency of the operation thereof can be improved. ## Claims ### Claim 1 A CMOS differential logic circuit using a voltage boosting technique, comprising: a precharge differential logic unit precharged to a source voltage in response to a clock signal and configured to output voltage having an increased load-driving ability by using a boosting voltage; a voltage-boosting unit pulled down by a ground voltage in response to the clock signal and configured to boost the pulled-down voltage by using capacitive coupling and output the boosting voltage; and a switching unit configured to couple the precharge differential logic unit and the voltage-boosting unit in response to the clock signal. ### Claim 2 (depends on 1) The CMOS differential logic circuit of claim 1, wherein the precharge differential logic unit comprises: first and second PMOS transistors configured to receive the source voltage through respective first terminals thereof, turned on in response to low-level of the clock signal, and configured to transfer the source voltages to first and second output nodes PB and P through respective second terminals thereof; and a differential logic tree precharged to the source voltage and configured to transfer the precharged voltage to the switching unit and increase inter-electrode voltages of first switching elements included in the differential logic tree by the boosting voltage. ### Claim 3 (depends on 2) The CMOS differential logic circuit of claim 2, wherein the precharge differential logic unit further comprises: a first inverter driver configured to invert a level of the voltage received from the first output node PB and output the voltage having the inverted level; and a second inverter driver configured to invert a level of the voltage received from the second output node P and output the voltage having the inverted level. ### Claim 4 (depends on 2) The CMOS differential logic circuit of claim 2, wherein: the first switching elements are NMOS transistors, and the inter-electrode voltages are gate-source voltages. ### Claim 5 (depends on 1) The CMOS differential logic circuit of claim 1, wherein the switching unit comprises a first NMOS transistor having a first terminal thereof, connected to the precharge differential logic unit and a second terminal thereof, connected to the voltage-boosting unit. ### Claim 6 (depends on 1) The CMOS differential logic circuit of claim 1, wherein the voltage-boosting unit comprises: a third PMOS transistor configured to receive the source voltage through a first terminal, turned on in response to low-level of the clock signal, and configured to transfer the source voltage to a first node NS connected to a second terminal of the third PMOS transistor; a second NMOS transistor configured to receive a ground voltage through a first terminal, turned on in response to high-level voltage at the first node NS, and transfer the ground voltage to a second node NP connected to a second terminal of the second NMOS transistor; a third NMOS transistor configured to have a first terminal connected to the ground voltage, turned on in response to high-level of the clock signal, and pull down the source voltage transferred to the first node NS connected to a second terminal of the third PMOS transistor; and a bootstrapped capacitor configured to have a first terminal connected to the first node NS and a second terminal connected to the second node NP and boosted by the boosting voltage in response to high-level of the clock signal, wherein the second node NP is connected to a second terminal of the switching unit. ### Claim 7 (depends on 1) The CMOS differential logic circuit of claim 1, wherein the boosting voltage is lower than 0 V. ### Claim 8 (depends on 6) The CMOS differential logic circuit of claim 6, wherein the voltage-boosting unit reduces a delay time attributable to a low source voltage by increasing voltage at the second node NP by the boosting voltage. ### Claim 9 (depends on 3) The CMOS differential logic circuit of claim 3, wherein the voltage-boosting unit increases load driving ability of the first and the second inverter drivers by increasing inter-electrode voltages of second switching elements included in the first and the second inverter drivers. ### Claim 10 (depends on 9) The CMOS differential logic circuit of claim 9, wherein: the second switching elements are PMOS transistors, and the inter-electrode voltages of the second switching elements are gate-source voltages.