# US 2014/0152341 A1 · External component-less pvt compensation scheme for io buffers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152341 A1 - Document ID: US20140152341A1 - Status: Published application - Kind: A1 - Application number: 13/706,110 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: LSI Corporation - Applicants: Lsi Corporation - Inventors: Anuroop Iyengar - Web page: https://patentgrep.com/patent/US20140152341A1 ## CPC - H03K 19/00369: {Modifications for compensating variations of temperature, supply voltage or other physical parameters} - H03K 3/011: Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature {(to maintain energy constant H03K3/015)} - H03K 19/00346: {Modifications for eliminating interference or parasitic voltages or currents} - H03K 19/00384: {in field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Disclosed is a system and method for providing Process-Voltage-Temperature (PVT) compensation for an Input/Output interface. An embodiment may connect an analog section and a digital section together to generate and measure an oscillation frequency (FOSC) used to look up a corresponding PVT control bit value in a look-up table. The analog section may be comprised of a voltage reduction system that reduces a bandgap reference voltage (VBGR) to half the supplied VBGR to a current mirror that supplies a PVT current (IPVT) to driver bit cells and a proportional mirrored control current (ICNTL) to a current controlled oscillator (CCO), which generates FOSC. The digital section may be used in combination with a frequency variable resistor and beta multiplier connected to the CCO to calibrate the capacitance of the CCO to tune out the process variation of the CCO capacitance and render FOSC to be linearly dependent on ICNTL. ## Claims ### Claim 1 A method to provide Process-Voltage-Temperature (PVT) compensation for an Input/Output (IO) interface, said IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), said method comprising: connecting said VBGR to a voltage reduction system; reducing said VBGR by substantially half at said voltage reduction system to produce VBGR/2; connecting said VBGR/2 to a current mirror system; connecting said current mirror system to a high supply voltage (VDD); connecting a driver bit cell to a low supply voltage (VSS); connecting said current mirror system to said driver bit cell such that a process-variable-temperature current (IPVT) flows through said driver bit cell; connecting said current mirror system to a compensated current controlled oscillator; mirroring said IPVT at said current mirror system such that said compensated current controlled oscillator receives a control current (ICNTL) that is proportional to said IPVT; generating an oscillation frequency (FOSC) at said compensated current controlled oscillator that is a function of said ICNTL; connecting said FOSC to a digital system; connecting said FREF to said digital system; measuring, by said digital system, a desired count period based on FREF; accumulating, by said digital system, a count of said FOSC at said digital system during said desired count period; looking up, by said digital system, a PVT control bit value that correlates to said accumulated count of said FOSC in a look-up table containing a predetermined correlation of potential count values of said FOSC to desired PVT control bit values; and providing, by said digital system, said looked up PVT control bit value to said IO interface. ### Claim 2 (depends on 1) The method of claim 1 further comprising: calculating, by said digital system, capacitor calibration bits; sending said capacitor calibration bits to said compensated current controlled oscillator; and calibrating capacitance of said compensated current controlled oscillator based on said capacitor calibration bits calculated by said digital system. ### Claim 3 (depends on 2) The method of claim 2 wherein said process of calibrating said compensated current controlled oscillator based on said capacitor calibration bits calculated by said digital system tunes said compensated current controlled oscillator such that said FOSC of said compensated current controller oscillator is substantially linearly dependent on said ICNTL, and further comprising digitally subtracting out an effect of channel length modulation of PMOS and NMOS devices in said compensated current controlled oscillator from said accumulated count value prior to said process of looking of said PVT control bit value. ### Claim 4 (depends on 2) The method of claim 2 wherein said process of calculating capacitor calibration bits by said digital system further comprises: connecting a first end of a capacitor resistor to said VBGR/2, said capacitor resistor being a variable resistor that varies as a function of FREF and of capacitance (CL) of said compensated current controlled oscillator; connecting a second end of said capacitor resistor to a beta multiplier system; connecting FREF to a frequency adjustment input of said capacitor resistor; connecting said beta multiplier system to an electrical switch; connecting said electrical switch to said compensated current controlled oscillator; closing said electrical switch to permit current flow of a calibration current (ICALIB) through said electrical switch that controls said compensated current controlled oscillator in place of said ICNTL such that said FOSC at said compensated current controlled oscillator is a function of ICALIB; measuring, by said digital system, said desired count period based on FREF; accumulating, by said digital system, said count of said FOSC for said ICALIB at said digital system during said desired count period; calculating, by said digital system, capacitor calibration bits as a function of a predetermined nominal FOSC value, a predetermined nominal CL value, and said FOSC for ICALIB. ### Claim 5 (depends on 4) The method of claim 4 wherein said process of calculating capacitor calibration bits by said digital system further comprises: simulating operation of said compensated current controlled oscillator at a nominal process corner; and predetermining said predetermined nominal FOSC value and said predetermined nominal CL value based on said simulated operation at said nominal process corner. ### Claim 6 (depends on 4) The method of claim 4 wherein said process of calculating capacitor calibration bits by said digital system further comprises closing said switch to perform said calculations of capacitor calibration bits at a power-on state of said IO interface or when a compensated current controlled oscillator calibration is requested during operation. ### Claim 7 (depends on 1) The method of claim 1 further comprising setting, by said IO interface, a buffer impedance of said IO interface in accord with said looked up PVT control bit value. ### Claim 8 (depends on 1) The method of claim 1 further comprising: simulating operation of said compensated current controlled oscillator from a slow process corner to a fast process corner in discrete steps correlating to each count in a range of accumulated counts during said desired count period; correlating each count in said range of accumulated counts to a desired PVT control bit value; and storing each count in said range of accumulated counts and said desired PVT control bit value correlating to each count in said range of accumulated counts in said look-up table containing said predetermined correlation of potential count values of said FOSC to desired PVT control bit values; ### Claim 9 (depends on 1) The method of claim 1 wherein said voltage reduction system is an op-amp loop and said method of claim 1 further comprises: connecting said VBGR to a positive input of an operational amplifier of said op-amp loop; connecting a negative input of said operational amplifier of said op-amp loop to said connection between said current mirror system and said driver bit cell; and setting a gain of said operational amplifier such that an output of said operational amplifier is at substantially said VBGR/2. ### Claim 10 (depends on 1) The method of claim 1 wherein said process of mirroring said IPVT at said current mirror system such that said compensated current controlled oscillator receives said ICNTL that is proportional to said IPVT makes said ICNTL proportional to said IPVT on a substantially one-to-one basis. ### Claim 11 A Process-Voltage-Temperature (PVT) compensation system for an Input/Output (IO) interface, said IO interface having a bandgap reference voltage (VBGR) and a reference frequency (FREF), said PVT compensation system comprising: a voltage reduction subsystem connected to said VBGR that reduces said VBGR by substantially half to produce VBGR/2; a driver bit cell connected to a current mirror subsystem and to a low supply voltage (VSS); said current mirror subsystem connected to said VBGR/2, to a high supply voltage (VDD), to said driver bit cell, and to a compensated current controlled oscillator such that a process-variable-temperature current (IPVT) flows through said driver bit cell and a mirrored control current (ICNTL) that is proportional to said IPVT is delivered to said compensated current controlled oscillator; a compensated current controlled oscillator connected to said ICNTL that generates an oscillation frequency (FOSC) that is a function of said ICNTL; a digital subsystem that is connected to said FOSC and to said FREF, and that measures a desired count period based on FREF, accumulates a count of said FOSC during said desired count period, looks up a PVT control bit value that correlates to said accumulated count of said FOSC in a look-up table containing a predetermined correlation of potential count values of said FOSC to desired PVT control bit values, and provides said looked up PVT control bit value to said IO interface in order for said IO interface to set a buffer impedance of said IO interface in accord with said looked up PVT control bit value. ### Claim 12 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said digital subsystem further calculates capacitor calibration bits and sends said capacitor calibration bits to said compensated current controlled oscillator, and, wherein said compensated current controlled oscillator calibrates capacitance of said compensated current controlled oscillator based on said capacitor calibration bits calculated by said digital system. ### Claim 13 (depends on 1) The Process-Voltage-Temperature (PVT) compensation system of claim 1 wherein said compensated current controlled oscillator is calibrated to tune said compensated current controlled oscillator such that said FOSC of said compensated current controller oscillator is substantially linearly dependent on said ICNTL, and wherein said digital subsystem digitally subtracts out an effect of channel length modulation of PMOS and NMOS devices in said compensated current controlled oscillator from said accumulated count value prior to looking up said PVT control bit value. ### Claim 14 (depends on 12) The Process-Voltage-Temperature (PVT) compensation system of claim 12 wherein said digital subsystem calculation of capacitor calibration bits further comprises: a capacitor resistor connected at a first end of a capacitor resistor to said VBGR/2, at a second end of said capacitor resistor to a beta multiplier subsystem, and at a frequency adjustment input of said capacitor resistor to FREF, said capacitor resistor being a variable resistor that varies as a function of FREF and of capacitance (CO of said compensated current controlled oscillator; said beta multiplier subsystem connected to said capacitor resistor and to an electrical switch; said electrical switch connected between said beta multiplier subsystem and said compensated current controlled oscillator such that when said electrical switch is closed a calibration current (ICALIB) flows through said electrical switch such that said ICALIB controls said compensated current controlled oscillator in place of said ICNTL and said FOSC at said compensated current controlled oscillator is a function of ICALIB; and wherein said digital system measures said desired count period based on FREF, accumulates said count of said FOSC for said ICALIB during said desired count period, and calculates capacitor calibration bits as a function of a predetermined nominal FOSC value, a predetermined nominal CL value, and said FOSC for ICALIB ### Claim 15 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said voltage reduction system is one of a group consisting of: an op-amp loop and a voltage divider circuit. ### Claim 16 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said voltage reduction system is an op-amp loop, and wherein said op-amp loop further comprises an operational amplified that is connected to said VBGR at a positive input of said operational amplifier and to said connection between said current mirror system and said driver bit cell at a negative input of said operational amplifier of said op-amp, and a gain of said operational amplifier is set such that an output of said operational amplifier is at substantially said VBGR/2. ### Claim 17 (depends on 1) The Process-Voltage-Temperature (PVT) compensation system of claim 1 wherein said current mirror subsystem makes said ICNTL proportional to said IPVT on a substantially one-to-one basis. ### Claim 18 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said compensated current controlled oscillator is comprised of a plurality of comb/fringe capacitors implemented using metal structures having substantially negligible voltage and temperature coefficients, said plurality of comb/fringe capacitors connected in a ring oscillator structure, said compensated current controlled oscillator also being digitally tunable. ### Claim 19 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said IO interface does not require an external precision resistor to perform PVT compensation. ### Claim 20 (depends on 11) The Process-Voltage-Temperature (PVT) compensation system of claim 11 wherein said VSS is substantially electric ground.