# US 2014/0152340 A1 · Operating method of input/output interface > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152340 A1 - Document ID: US20140152340A1 - Status: Published application - Kind: A1 - Application number: 14/093,916 - Filed: 2013-12-02 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Young Chul CHO; Jung Bae LEE; Jung Hwan CHOI - Web page: https://patentgrep.com/patent/US20140152340A1 ## CPC - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G05F 1/625: wherein it is irrelevant whether the variable actually regulated is AC or DC - G06F 1/3287: by switching off individual functional units in the computer system - G06F 13/4068: {Electrical coupling} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - H03K 19/0005: {Modifications of input or output impedance} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and outputting a data signal using the selected one of the plurality of output driver circuits. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. Another method of operating an includes generating a mode selection signal based on a received command signal, and controlling an ODT circuit included in the input/output interface according to the mode selection signal. ## Claims ### Claim 1 A method of operating an input/output interface comprising: selecting, by an output block of the input/output interface, one of a plurality of output driver circuits according to a mode selection signal, the mode selection signal being a control signal for controlling an on-die termination (ODT) circuit included in the input/output interface; and outputting a data signal using the selected one of the plurality of output driver circuits. ### Claim 2 (depends on 1) The method of claim 1, before the selecting, further comprising: generating the mode selection signal according to memory latency. ### Claim 3 (depends on 2) The method of claim 2, wherein the memory latency is one of a read latency and a write latency. ### Claim 4 (depends on 1) The method of claim 1, before the selecting, further comprising: generating the mode selection signal based on a mode register set (MRS) command, the MRS command being used to adjust an operation frequency of the ODT circuit. ### Claim 5 (depends on 1) The method of claim 1, wherein the selecting selects, one of the output driver circuits including a NMOS pull-up transistor when the mode selection signal indicates an operation mode for a high speed operation, and one of the output driver circuits including a PMOS pull-up transistor is selected when the mode selection signal indicates an operation mode for a low speed operation. ### Claim 6 (depends on 1) The method of claim 1, further comprising: selecting one of a plurality of termination levels of the ODT circuit according to the mode selection signal. ### Claim 7 (depends on 6) The method of claim 6, wherein the plurality of termination levels include a supply voltage level, a ground voltage level, and a medium level between the supply voltage level and the ground voltage level. ### Claim 8 A method of operating an input/output interface comprising: selecting, by an input receiver block of the input/output interface, one of a plurality of input receiver circuits according to a mode selection signal; and receiving a data signal using the selected input receiver circuit. ### Claim 9 (depends on 8) The method of claim 8, wherein the mode selection signal is a control signal for controlling an on-die termination (ODT) circuit included in the input/output interface. ### Claim 10 (depends on 8) The method of claim 8, before the selecting, further comprising: generating the mode selection signal according to memory latency, the memory latency including read latency and write latency. ### Claim 11 (depends on 8) The method of claim 8, further comprising: generating, before the selecting, the mode selection signal based on a mode register set (MRS) command, the MRS command being used to adjust a memory operation frequency. ### Claim 12 (depends on 8) The method of claim 8, wherein the selecting selects a different input receiver circuit when the mode selection signal indicates an operation mode for a high speed operation and than when the mode selection signal indicates an operation mode for a low speed operation. ### Claim 13 (depends on 8) The method of claim 8, wherein the selecting selects at least one of the plurality of input receiver circuits having a plurality of stages when the mode selection signal indicates an operation mode for a high speed operation. ### Claim 14 (depends on 8) The method of claim 8, wherein the selecting selects at least one of the plurality of input receiver circuits having different types of MOS transistors when the mode selection signal indicates an operation mode for a low speed operation, the different types of MOS transistors being connected to each other in series. ### Claim 15 (depends on 8) The method of claim 8, further comprising: selecting one of a plurality of sense amplifier flip-flops according to the mode selection signal. ### Claim 16 A method of operating an input/output interface comprising: generating, by a controller of a memory device, a mode selection signal based on a received command signal; and controlling, by the controller, an on-die termination (ODT) circuit included in the input/output interface according to the mode selection signal. ### Claim 17 (depends on 16) The method of claim 16, wherein the controller includes a mode register configured to store operation mode data for controlling the memory device, the operation mode data including memory latency data and operation frequency data, the memory latency data indicating a memory latency of the memory device, the operation frequency data indicating an operation frequency of the memory device. ### Claim 18 (depends on 17) The method of claim 17, wherein the generating the mode selection signal is further based on the operation frequency data. ### Claim 19 (depends on 17) The method of claim 17, wherein the generating the mode selection signal is further based on the memory latency data. ### Claim 20 (depends on 16) The method of claim 16, further comprising: selecting one of a plurality of output driver circuits according to the mode selection signal; and outputting a data signal using the selected one of the plurality of output driver circuits.