# US 2014/0152334 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152334 A1 - Document ID: US20140152334A1 - Status: Published application - Kind: A1 - Application number: 14/077,277 - Filed: 2013-11-12 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kazuyuki Ito; Hiroshi Shirota - Web page: https://patentgrep.com/patent/US20140152334A1 ## CPC - H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - G01R 31/27: Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements {(testing printed circuit boards G01R31/2801)} - G01R 31/2832: {Specific tests of electronic circuits not provided for elsewhere (G01R31/2801, G01R31/316 take precedence)} - G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)} - G01R 31/31725: {Timing aspects, e.g. clock distribution, skew, propagation delay (for tester hardware G01R31/31937)} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract If an exclusive OR circuit itself, a component of a signal delay detecting circuit, has failed to operate properly, a signal delay cannot be detected accurately. A malfunction pre-detecting circuit 12 includes a delay circuit DL to delay input data that is input in parallel to a data input terminal of a flip-flop FF1 provided in a subsequent stage of a flip-flop FF0, a flip-flop FFT that receives output of the delay circuit DL, and a comparator CMP that compares output of the flip-flop FF1 and output of the flip-flop FFT. Test data tv1 and test data tv2 are input to the malfunction pre-detecting circuit 12 in an operation test mode for testing operation of the malfunction pre-detecting circuit 12. The test data tv2 is input to the delay circuit DL. The comparator CMP compares the test data tv1 and output of the flip-flop FFT in the operation test mode. ## Claims ### Claim 1 A semiconductor device comprising: a first flip-flop; a second flip-flop which is provided in a subsequent stage of the first flip-flop; and a malfunction pre-detecting circuit provided on a route branching off from a route to a data input terminal of the second flip-flop, the malfunction pre-detecting circuit comprising: a delay element to delay input data that is input in parallel to the data input terminal of the second flip-flop; a third flip-flop that receives output of the delay element; and a comparator that compares output of the second flip-flop and output of the third flip-flop, wherein first test data and second test data are input to the malfunction pre-detecting circuit in an operation test mode for testing operation of the malfunction pre-detecting circuit and the second test data is input to the delay element, and wherein the comparator compares the first test data and output of the third flip-flop in the operation test mode. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the malfunction pre-detecting circuit comprises: a first selector that outputs said second test data to the delay element in the operation test mode and outputs said input data to the delay element in usual operation mode; and a second selector that outputs said first test data to the comparator in the operation test mode and outputs the output of the second flip-flop to the comparator in the usual operation mode. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the semiconductor device comprises a switch for stopping power supply to the first flip-flop and the second flip-flop, if both compared by the comparator are out of phase. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the semiconductor device comprises a plurality of circuit blocks, each operating on a separate power supply voltage, and wherein the switch stops power supply to a circuit block including the first flip-flop and the second flip-flop, if both compared by the comparator are out of phase. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the semiconductor device is a microcomputer of dual core lockstep architecture, comprising: a first CPU core; a second CPU core; and a comparator that compares a result of computation by the first CPU core and a result of computation by the second CPU core. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein an interrupt is notified to the first CPU core and the second CPU core, if both compared by the comparator are out of phase, and wherein the first CPU core controls the switch to stop power supply. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, wherein a signal representing a comparison result of the comparator is sent directly to the switch to stop the power supply. ### Claim 8 (depends on 4) The semiconductor device according to claim 4, wherein a signal representing a comparison result of the comparator is sent to an entity external to the semiconductor device and the power supply is caused to stop by control of the external entity. ### Claim 9 A semiconductor device comprising: a first flip-flop; a second flip-flop which is provided in a subsequent stage of the first flip-flop; and a malfunction pre-detecting circuit provided on a route branching off from a route to a data input terminal of the second flip-flop, the malfunction pre-detecting circuit comprising: a plurality of stages of delay elements coupled in series to delay input data that is input in parallel to the data input terminal of the second flip-flop; a plurality of third flip-flops, each receiving output of each delay element; a plurality of comparators, each comparing output of the second flip-flop and output of a third flip-flop linked thereto, wherein first test data and second test data are input to the malfunction pre-detecting circuit in an operation test mode for testing operation of the malfunction pre-detecting circuit and the second test data is input to a first stage of the stages of delay elements, and wherein the comparators each compare the first test data and output of the third flip-flop linked thereto in the operation test mode.