# US 2014/0152278 A1 · Systems and methods for switched-inductor integrated voltage regulators > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0152278 A1 - Document ID: US20140152278A1 - Status: Published application - Kind: A1 - Application number: 14/172,210 - Filed: 2014-02-04 - Published: 2014-06-05 - Earliest claimed: 2011-08-26 - Assignees: The Trustees of Columbia University in the City of New York - Applicants: The Trustees of Columbia University in the City of New York - Inventors: Kenneth L. Shepard; Noah Andrew Sturcken - Web page: https://patentgrep.com/patent/US20140152278A1 ## CPC - H02M 3/1584: {with a plurality of power processing stages connected in parallel} - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Power controller includes an output terminal having an output voltage, at least one clock generator to generate a plurality of clock signals and a plurality of hardware phases. Each hardware phase is coupled to the at least one clock generator and the output terminal and includes a comparator. Each hardware phase is configured to receive a corresponding one of the plurality of clock signals and a reference voltage, combine the corresponding clock signal and the reference voltage to produce a reference input, generate a feedback voltage based on the output voltage, compare the reference input and the feedback voltage using the comparator and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. An integrated circuit including the power controller is also provided. ## Claims ### Claim 1 A power controller, comprising: an output terminal having an output voltage; at least one clock generator to generate a plurality of clock signals; a plurality of hardware phases, each hardware phase being coupled to the at least one clock generator and the output terminal and including a comparator, each hardware phase being configured to: receive a corresponding one of the plurality of clock signals and a reference voltage; combine the corresponding clock signal and the reference voltage to produce a reference input; generate a feedback voltage based on the output voltage; compare the reference input and the feedback voltage using the comparator; and provide a comparator output to the output terminal, whereby the comparator output determines a duty cycle of the power controller. ### Claim 2 (depends on 1) The power controller of claim 1, wherein the plurality of hardware phases comprise four hardware phases. ### Claim 3 (depends on 1) The power controller of claim 1, wherein the plurality of hardware phases comprise unlatched hardware phases. ### Claim 4 (depends on 1) The power controller of claim 1, wherein each of the plurality of clock signals have a different phase. ### Claim 5 (depends on 1) The power controller of claim 1, wherein the reference input comprises a triangle wave potential. ### Claim 6 (depends on 5) The power controller of claim 5, wherein the triangle wave potential is centered at a desired DC output voltage of the power controller. ### Claim 7 (depends on 1) The power controller of claim 1, further comprising a bridge switching node having a bridge switching node voltage, the feedback voltage being further based on the bridge switching node voltage. ### Claim 8 (depends on 7) The power controller of claim 7, wherein the bridge switching node voltage is determined from an inductor current of the bridge switching node. ### Claim 9 (depends on 1) The power controller of claim 1, wherein the comparator is an unlatched continuous comparator. ### Claim 10 (depends on 1) An integrated circuit chip comprising the power controller of claim 1. ### Claim 11 (depends on 10) The integrated circuit chip of claim 10, further comprising one or more network-on-chip coupled to the power controller. ### Claim 12 (depends on 11) The integrated circuit chip of claim 11, wherein the one or more network-on-chip comprises four networks-on-chip, each network-on-chip having 64 cores. ### Claim 13 A method comprising: for each one of a plurality of hardware phases, each hardware phase being coupled to at least one clock generator and an output terminal and including a comparator: receiving a corresponding one of a plurality of clock signals from the at least one clock generator and a reference voltage; combining the corresponding clock signal and the reference voltage to produce a reference input; generating a feedback voltage based on an output voltage from an output terminal; comparing the reference input and the feedback voltage using the comparator; and providing a comparator output to the output terminal, whereby the comparator output determines a duty cycle of a power controller. ### Claim 14 (depends on 13) The method of claim 13, further comprising providing the plurality of clock signals, each of the plurality of clock signals having a different phase. ### Claim 15 (depends on 13) The method of claim 13, further comprising providing the reference input, wherein the reference input comprises a triangle wave potential. ### Claim 16 (depends on 15) The method of claim 15, wherein providing the reference input comprises centering the triangle wave potential at a desired DC output voltage of the power controller. ### Claim 17 (depends on 13) The method of claim 13, generating the feedback voltage further comprises generating the feedback voltage based on a bridge switching node voltage from a bridge switching node. ### Claim 18 (depends on 17) The method of claim 17, further comprising determining the bridge switching node voltage from an inductor current of the bridge switching node.