# US 2014/0151901 A1 · Method for manufacturing semiconductor device, semiconductor device and jig for forming wiring > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151901 A1 - Document ID: US20140151901A1 - Status: Published application - Kind: A1 - Application number: 14/176,211 - Filed: 2014-02-10 - Published: 2014-06-05 - Earliest claimed: 2011-08-11 - Assignees: Tokyo Electron Limited - Applicants: Tokyo Electron Limited - Inventors: Haruo IWATSU; Toshiyuki Matsumoto - Web page: https://patentgrep.com/patent/US20140151901A1 ## CPC - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10D 88/00: Three-dimensional [3D] integrated devices - H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating - H10P 72/74: {using temporarily an auxiliary support} - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/031: {of conductive parts of the interconnections} - H10W 20/067: {by modifying the pattern of conductive parts} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/212: {Top-view shapes or dispositions, e.g. top-view layouts of the vias} - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 90/00: Package configurations - H10P 72/7416: {used during dicing or grinding} - H10P 72/7422: {used to protect an active side of a device or wafer} - H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer} - H10W 46/403: {for non-wireless electrical read out} - H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - Y10T 29/532: Conductor - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A method for manufacturing a semiconductor device includes: forming a structure including a substrate, a device layer formed on the substrate, a pair of through-hole electrodes penetrating through the substrate in the thickness direction of the substrate, a pair of vertical electrodes extending in the thickness direction of the substrate and reaching to one surface of the substrate, and a shared wiring connecting the pair of vertical electrodes in the device layer; forming a connection wiring connecting one of the through-hole electrodes and one of the vertical electrodes; and stacking the structure and a second substrate such that an electrode of the second substrate is connected to a through-hole electrode which is not connected to the connection wiring among the pair of through-hole electrodes. ## Claims ### Claim 1 A method for manufacturing a semiconductor device, comprising: forming a structure comprising a substrate, a device layer formed on the substrate, a pair of through-hole electrodes penetrating through the substrate in a thickness direction of the substrate, a pair of vertical electrodes extending in the thickness direction of the substrate and reaching to one surface of the substrate, and a shared wiring connecting the pair of vertical electrodes in the device layer; forming a connection wiring connecting one of the through-hole electrodes and one of the vertical electrodes; and stacking the structure and a second substrate such that an electrode of the second substrate is connected to a through-hole electrode which is not connected to the connection wiring among the pair of through-hole electrodes. ### Claim 2 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the structure comprises forming a second shared wiring connecting the pair of through-hole electrodes in the device layer and forming a device-side bump connected to the second shared wiring and connecting to a surface of the device layer, the stacking of the structure and the second substrate comprises laminating the structure and the second substrate such that the electrode of the second substrate is connected to the device-side bump, and the electrode of the second substrate is a through-hole electrode which is not connected to a connection wiring of the second substrate among a pair of through-hole electrodes penetrating through the second substrate. ### Claim 3 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the structure comprises forming in the device layer a circuit connecting to the shared wiring. ### Claim 4 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the connection wiring comprises positioning a template comprising a pair of first electrodes positioned to correspond to the pair of through-hole electrodes and configured to switch polarity and a pair of second electrodes positioned to correspond to the pair of vertical electrodes and configured to switch polarity, and applying voltage between one of the through-hole electrodes and one of the vertical electrodes through one of the first electrodes and one of the second electrodes, respectively, with different polarities such that the connection wiring comprising plating is formed between the one of the through-hole electrodes and the one of the vertical electrodes. ### Claim 5 (depends on 4) The method for manufacturing a semiconductor device according to claim 4, further comprising applying voltage between an auxiliary electrode and one of the first electrodes and the second electrodes with different polarities after the applying of voltage between one of the through-hole electrodes and one of the vertical electrodes, wherein the template has the auxiliary electrode positioned between the one of the through-hole electrodes and the one of the vertical electrodes. ### Claim 6 (depends on 4) The method for manufacturing a semiconductor device according to claim 4, further comprising hydrophilizing at least a region of a surface of the substrate prior to the forming of the connection wiring such that the region becomes more hydrophilic with respect to the other region of the surface and that the connection wiring comprising plating is formed in the region. ### Claim 7 (depends on 1) The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the structure comprises forming the through-hole electrodes and the vertical electrodes such that the through-hole electrodes and the vertical electrodes include a through-hole electrode and a vertical electrode positioned adjacent to each other and having protruding portions facing each other, respectively. ### Claim 8 A semiconductor device, comprising: a plurality of substrates stacked one another and including at least one substrate comprising a device layer formed on the substrate, a pair of through-hole electrodes penetrating through the substrate in a thickness direction of the substrate, a pair of vertical electrodes extending through the substrate in the thickness direction of the substrate and reaching to one surface of the substrate, and a shared wiring connecting the pair of vertical electrodes in the device layer; and a connection wiring connecting one of the through-hole electrodes and one of the vertical electrodes. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the device layer has a second shared wiring connecting the pair of through-hole electrodes and a device side bump connected to the second shared wiring and connecting to a surface of the device layer. ### Claim 10 (depends on 8) The semiconductor device according to claim 8, wherein the device layer has a circuit connected to the shared wiring. ### Claim 11 (depends on 8) The semiconductor device according to claim 8, further comprising: a template positioned on the substrate and comprising a pair of first electrodes positioned to correspond to the pair of through-hole electrodes and configured to switch polarity and a pair of second electrodes positioned to correspond to the pair of vertical electrodes and configured to switch polarity, wherein the connection wiring is formed by applying voltage between one of the through-hole electrodes and one of the vertical electrodes through one of the first electrodes and one of the second electrodes, respectively, with different polarities such that the connection wiring comprising plating is formed between the one of the through-hole electrodes and the one of the vertical electrodes. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the template has an auxiliary electrode positioned between one of the through-hole electrodes and one of the vertical electrodes, and the connection wiring is formed by applying voltage between the one of the through-hole electrodes and the one of the vertical electrodes through one of the first electrodes and one of the second electrodes, respectively, with different polarities and applying voltage between the auxiliary electrode and one of the first electrodes and the second electrodes with different polarities after the applying of voltage between the one of the through-hole electrodes and the one of the vertical electrodes such that the connection wiring comprising plating is formed between the one of the through-hole electrodes and the one of the vertical electrodes. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, wherein the substrate has a surface including a region which is more hydrophilic with respect to the other region of the surface and in which the connection wiring comprising plating is formed. ### Claim 14 (depends on 8) The semiconductor device according to claim 8, wherein the through-hole electrodes and the vertical electrodes include a through-hole electrode and a vertical electrode positioned adjacent to each other and having protruding portions facing each other, respectively. ### Claim 15 A wiring-forming jig for forming wiring on a surface of a substrate, comprising: a base body having a surface configured to face a substrate; and a plurality of opposed electrodes positioned on the surface of the base body such that the plurality of opposed electrodes faces a plurality of electrodes exposed on a surface of the substrate, wherein the plurality of opposed electrodes includes at least one electrode configured to switch polarity. ### Claim 16 (depends on 15) The wiring-forming jig for forming wiring according to claim 15, further comprising an auxiliary electrode positioned between two adjacent electrodes of the opposed electrodes on the surface of the base body.