# US 2014/0151900 A1 · Stacked packaging using reconstituted wafers

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- Number: US 2014/0151900 A1
- Document ID: US20140151900A1
- Status: Published application
- Kind: A1
- Application number: 14/175,985
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2011-12-14
- Assignees: Broadcom Corporation
- Applicants: Broadcom Corporation
- Inventors: Kevin Kunzhong HU; Sam Ziqun Zhao; Rezaur Rahman Khan; Pieter Vorenkamp; Sampath K.V. Karikalan; Xiangdong Chen
- Web page: https://patentgrep.com/patent/US20140151900A1

## CPC

- H10W 90/00: Package configurations
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/354: {comprising polymers}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/20: Configurations of stacked chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.

## Claims

### Claim 1

A stacked package comprising:
a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer;
said top die and said bottom die being insulated from one another by an insulation arrangement;
said top die and said bottom die being interconnected through said insulation arrangement.

### Claim 2 (depends on 1)

The stacked package of claim 1, wherein said top die and said bottom die are interconnected through a conductive via.

### Claim 3 (depends on 2)

The stacked package of claim 2, wherein said conductive via extends within said insulation arrangement.

### Claim 4 (depends on 1)

The stacked package of claim 1, wherein said top die has a top redistribution layer, and said bottom die has a bottom redistribution layer that is connected to said top redistribution layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein said insulation arrangement comprises a top molding compound that flanks said top die and a bottom molding compound that flanks said bottom die.

### Claim 6 (depends on 5)

The method of claim 5, wherein said top molding compound is situated over said bottom molding compound.

### Claim 7 (depends on 1)

The method of claim 1, wherein said insulation arrangement comprises a top molding compound that flanks said top die, said top die and said bottom die being interconnected through at least said top molding compound.

### Claim 8

A method for manufacturing a stacked package, said method comprising:
stacking a top reconstituted wafer having a top die over a bottom reconstituted wafer having a bottom die to form a reconstituted wafer stack;
interconnecting said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer through an insulation arrangement;
singulating said reconstituted wafer stack to form said stacked package.

### Claim 9 (depends on 8)

The method of claim 8, wherein said interconnecting comprises forming a conductive via through said insulation arrangement.

### Claim 10 (depends on 8)

The method of claim 8, wherein said insulation arrangement comprises a top molding compound that flanks said top die of said top reconstituted wafer and a bottom molding compound that flanks said bottom die of said bottom reconstituted wafer.

### Claim 11 (depends on 10)

The method of claim 10, wherein said top molding compound is situated over said bottom molding compound.

### Claim 12 (depends on 8)

The method of claim 8, further comprising forming a package terminal for connection to said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer prior to said singulating.

### Claim 13 (depends on 8)

The method of claim 8, wherein said stacking comprises adhering said top reconstituted wafer to said bottom reconstituted wafer using a passivation layer.

### Claim 14

A method for manufacturing a stacked package, said method comprising:
stacking a top reconstituted wafer having a top die over a bottom reconstituted wafer having a bottom die to form a reconstituted wafer stack, said top die having a top redistribution layer, and said bottom die having a bottom redistribution layer;
interconnecting said top die of said top reconstituted wafer and said bottom die of said bottom reconstituted wafer by connecting said top redistribution layer to said bottom redistribution layer;
singulating said reconstituted wafer stack to form said stacked package.

### Claim 15 (depends on 14)

The method of claim 14, wherein said interconnecting comprises forming a conductive via through said top redistribution layer.

### Claim 16 (depends on 14)

The method of claim 14, wherein said interconnecting comprises forming a conductive via through said bottom redistribution layer.

### Claim 17 (depends on 14)

The method of claim 14, wherein said interconnecting is through an insulation arrangement.

### Claim 18 (depends on 14)

The method of claim 14, further comprising forming a package terminal for connection to said top die and said bottom die prior to said singulating.

### Claim 19 (depends on 14)

The method of claim 14, wherein said stacking comprises adhering said top reconstituted wafer to said bottom reconstituted wafer using a passivation layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein said passivation layer is a bottom redistribution layer passivation.