# US 2014/0151899 A1 · Dual-damascene process to fabricate thick wire structure

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- Number: US 2014/0151899 A1
- Document ID: US20140151899A1
- Status: Published application
- Kind: A1
- Application number: 14/166,274
- Filed: 2014-01-28
- Published: 2014-06-05
- Earliest claimed: 2006-01-19
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Douglas D. COOLBAUGH; Keith E. DOWNES; Peter J. LINDGREN; Anthony K. STAMPER
- Web page: https://patentgrep.com/patent/US20140151899A1

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/692: {Electrodes}
- H10W 20/0888: {wherein via-level dielectrics are compositionally different than trench-level dielectrics}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method and a semiconductor device are provided. The semiconductor device includes a partial via etched in a stacked structure and a trough above the partial via. The method includes performing thick wiring using selective etching while etching the partial via to an etch stop layer.

## Claims

### Claim 1

A stacked structure comprising:
a first etch stop layer on a metal layer;
a second etch stop layer below the metal layer;
a first partial via extending to the first etch stop layer on the metal layer;
a second partial via extending to the second etch stop layer;
a first wire trough above the first partial via and; and
a second wire trough above the second partial via.

### Claim 2 (depends on 1)

The stacked structure of claim 1, wherein the metal layer is an Mx-1 metal layer.

### Claim 3 (depends on 1)

The stacked structure of claim 1, wherein the second etch stop layer is on a metal insulator metal (MIM) capacitor.

### Claim 4 (depends on 1)

The stacked structure of claim 1, wherein:
the stacked structure further comprises a third etch stop layer above the first etch stop layer; and
the first wire trough and the second wire trough extend to the third etch stop layer.

### Claim 5 (depends on 1)

The stacked structure of claim 1, wherein:
the first etch stop layer is on a first low K dielectric layer and contacts an upper surface of a damascene copper wire formed in the first low K dielectric layer;
the stacked structure further comprises:
an interlevel dielectric layer and a second low K dielectric layer on the first etch stop layer;
a third etch stop layer on the second low K dielectric layer; and
a third low K dielectric layer on the third etch stop layer.

### Claim 6 (depends on 5)

The stacked structure of claim 5 further comprising an MIM capacitor embedded in the interlevel dielectric layer.

### Claim 7 (depends on 5)

The stacked structure of claim 5, wherein the MIM capacitor is comprised of a plurality of plates, the plurality of plates including at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride, and silicon carbide etch stop layer.

### Claim 8 (depends on 1)

The stacked structure of claim 1, wherein the second etch stop layer has a thickness about twice a thickness of the first etch stop layer.

### Claim 9 (depends on 1)

The stacked structure of claim 1, wherein the first etch stop layer and the third etch stop layer are at least one of silicon nitride, silicon carbo nitride, silicon oxy carbo nitride, and silicon carbide.

### Claim 10 (depends on 1)

The stacked structure of claim 1, wherein the first partial via is aligned with the metal layer.

### Claim 11 (depends on 1)

The stacked structure of claim 1, wherein the second partial via is aligned with the MIM capacitor.

### Claim 12

A dual-damascene copper BEOL structure, comprising:
a first partial height via over at least an underlying metal layer, the first partial height via extending to about a first etch stop layer on the underlying metal layer;
a second partial height via over a MIM capacitor, the second partial height via extending to about a second etch stop layer on the MIM capacitor;
a first wire trough above the first partial height via; and
a second wire trough above the second partial height via.

### Claim 13 (depends on 12)

The dual-damascene copper BEOL structure of claim 12, wherein:
the dual-damascene copper BEOL structure further comprises a first low K dielectric layer;
the underlying metal is in the first low K dielectric layer; and
the first etch stop layer is on the first low K dielectric layer and contacts an upper surface of the underlying metal layer.

### Claim 14 (depends on 12)

The dual-damascene copper BEOL structure of claim 12, further comprising:
a second low K dielectric layer and an interlevel dielectric layer on the first etch stop layer, wherein:
the MIM capacitor is embedded in the interlevel dielectric layer, and
the second etch stop layer is on the MIM capacitor;
a third etch stop layer on the second low K dielectric layer; and
a third low K dielectric layer on the third etch stop layer.

### Claim 15 (depends on 14)

The dual-damascene copper BEOL structure of claim 14, wherein the first etch stop layer and the third etch stop layer are at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride and silicon carbide etch stop layer.

### Claim 16 (depends on 12)

The dual-damascene copper BEOL structure of claim 12, wherein the second etch stop layer has a thickness about twice a thickness of the first etch stop layer.

### Claim 17 (depends on 12)

The dual-damascene copper BEOL structure of claim 12, wherein the MIM capacitor comprises a plurality of plates, the plurality of plates including at least one of a silicon nitride, silicon carbo nitride, silicon oxy carbo nitride, and silicon carbide etch stop.