# US 2014/0151894 A1 · Far back end of the line stack encapsulation

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- Number: US 2014/0151894 A1
- Document ID: US20140151894A1
- Status: Published application
- Kind: A1
- Application number: 13/693,749
- Filed: 2012-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Tymon Barwicz; Robert L. Bruce; Swetha Kamlapurkar
- Web page: https://patentgrep.com/patent/US20140151894A1

## CPC

- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for far back end of the line (FBEOL) protection of a semiconductor device includes forming a patterned layer over a back end of the line (BEOL) stack, depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer. A resist layer is patterned over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer. The first conformal protection layer is etched through the openings in the resist layer to form extended openings that reach a stop position. The resist layer is removed, and a second conformal protection layer is formed on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

## Claims

### Claim 1

A method for far back end of a line (FBEOL) protection of a semiconductor device, comprising:
forming a patterned layer over a back end of a line (BEOL) stack;
depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of openings formed in the patterned layer;
patterning a resist layer over the first conformal protection layer such that openings in the resist layer correspond with the openings in the patterned layer;
etching the first conformal protection layer through the openings in the resist layer to form extended openings that reach a stop position;
removing the resist layer; and
depositing a second conformal protection layer on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary to protect at least the patterned layer and a portion of the BEOL stack.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein depositing a first conformal protection layer on the patterned layer includes depositing the first conformal protection layer using a dielectric deposited at temperatures below 400 degrees C.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein etching the first conformal protection layer includes etching the first conformal protection layer with an anisotropic etching process to break through the first conformal protection layer and extend the openings.

### Claim 4 (depends on 1)

The method as recited in claim 1, wherein the stop position includes a position within the BEOL stack.

### Claim 5 (depends on 1)

The method as recited in claim 1, wherein the stop position includes a position within a front end of the line (FEOL) stack below the BEOL stack.

### Claim 6 (depends on 1)

The method as recited in claim 1, wherein the stop position includes a position to a substrate below a front end of the line (FEOL) stack and below the BEOL stack.

### Claim 7 (depends on 1)

The method as recited in claim 1, wherein depositing a second conformal protection layer includes depositing the second conformal protection layer using a dielectric deposited at temperatures below 400 degrees C.

### Claim 8 (depends on 1)

The method as recited in claim 1, further comprising etching the second conformal protection layer through the extended openings to expose a surface at the stop position.

### Claim 9 (depends on 8)

The method as recited in claim 8, further comprising forming contacts through the extended openings to the surface at the stop position.

### Claim 10 (depends on 8)

The method as recited in claim 8, further comprising wet etching during further processing such that the encapsulation boundary protects at least the patterned layer and the portion of the BEOL stack.

### Claim 11 (depends on 1)

The method as recited in claim 1, wherein the patterned layer includes polyimide.

### Claim 12

A method for far back end of a line (FBEOL) protection of a semiconductor device, comprising:
forming first openings in a patterned layer over a back end of a line (BEOL) stack;
depositing a first conformal protection layer on the patterned layer which covers horizontal surfaces of a top surface and sidewalls of the first openings formed in the patterned layer;
patterning a resist layer over the first conformal protection layer to form second openings in the resist layer that correspond with the first openings in the patterned layer;
etching the first conformal protection layer through the first and second openings to form extended openings that reach a stop position;
removing the resist layer;
depositing a second conformal protection layer on the first conformal protection layer and on sidewalls of the extended openings to form an encapsulation boundary; and
wet etching during further processing such that the encapsulation boundary protects at least the patterned layer and a portion of the BEOL stack.

### Claim 13 (depends on 12)

The method as recited in claim 12, wherein depositing a first conformal protection layer on the patterned layer includes depositing the first conformal protection layer using a dielectric deposited at temperatures below 400 degrees C.

### Claim 14 (depends on 12)

The method as recited in claim 12, wherein etching the first conformal protection layer includes etching the first conformal protection layer with an anisotropic etching process to break through the first conformal protection layer and extend the openings.

### Claim 15 (depends on 12)

The method as recited in claim 12, wherein the stop position includes a position within the BEOL stack.

### Claim 16 (depends on 12)

The method as recited in claim 12, wherein the stop position includes a position within a front end of line (FEOL) stack below the BEOL stack.

### Claim 17 (depends on 12)

The method as recited in claim 12, wherein the stop position includes a position to a substrate below a front end of the line (FEOL) stack and below the BEOL stack.

### Claim 18 (depends on 12)

The method as recited in claim 12, wherein depositing a second conformal protection layer includes depositing the second conformal protection layer using a dielectric deposited at temperatures below 400 degrees C.

### Claim 19 (depends on 12)

The method as recited in claim 12, further comprising etching the second conformal protection layer through the extended openings to expose a surface at the stop position.

### Claim 20 (depends on 19)

The method as recited in claim 19, further comprising forming contacts through the extended openings to the surface at the stop position.

### Claim at position 21

21-27. (canceled)