# US 2014/0151889 A1 · Techniques for enhancing dielectric breakdown performance

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0151889 A1
- Document ID: US20140151889A1
- Status: Published application
- Kind: A1
- Application number: 13/693,602
- Filed: 2012-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Intel Corporation
- Inventors: Pavel S. Plekhanov; Kevin J. Fischer; Qiang Fu; Hiroki Hiramatsu
- Web page: https://patentgrep.com/patent/US20140151889A1

## CPC

- H10W 72/00: Interconnections or connectors in packages
- H10W 20/01: {Manufacture or treatment}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/48: Insulating materials thereof
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material. In some instances, such a layer may serve as an etch stop.

## Claims

### Claim 1

An integrated circuit comprising:
a first dielectric layer having formed therein:
a first interconnect;
a second interconnect adjacent to the first interconnect; and
a recess positioned between the first and second interconnects; and
a second dielectric layer deposited over a topology formed by the recess and the first and second interconnects, wherein the second dielectric layer comprises a material of higher dielectric breakdown field (Ec) than the first dielectric layer.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the first dielectric layer comprises carbon-doped silicon dioxide (C-doped SiO2) having a carbon concentration in the range of about 0% to 30%.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein at least one of the first and/or second interconnects comprises at least one of copper (Cu), silver (Ag), aluminum (Al), gold (Au), and/or an alloy of any of the aforementioned.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer comprises at least one of silicon nitride (Si3N4), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), and/or a combination of any of the aforementioned.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer is conformal to the topology.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, wherein a first portion of the second dielectric layer has a first thickness and a second portion of the second dielectric layer has a second thickness that is different from the first thickness.

### Claim 7 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer has a thickness in the range of about 1-100 nm.

### Claim 8 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer encapsulates high-electric field points of the first and second interconnects so as to inhibit a voltage breakdown path there between through the first dielectric layer.

### Claim 9 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer provides a hermetic seal for at least one of the first and/or second interconnects.

### Claim 10 (depends on 1)

The integrated circuit of claim 1, wherein at least one of the first and/or second interconnects comprises an electrically conductive metal, and wherein the second dielectric layer reduces diffusion of the electrically conductive metal into the first dielectric layer.

### Claim 11 (depends on 1)

The integrated circuit of claim 1, wherein the second dielectric layer serves as an etch stop layer.

### Claim 12 (depends on 1)

The integrated circuit of claim 1 further comprising an intermediate layer disposed between the first dielectric layer and at least one of the first and/or second interconnects.

### Claim 13 (depends on 12)

The integrated circuit of claim 12, wherein the intermediate layer comprises at least one of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), and/or titanium nitride (TiN).

### Claim 14 (depends on 1)

The integrated circuit of claim 1 further comprising a third dielectric layer deposited over a topology formed by the second dielectric layer.

### Claim 15

A method of forming an integrated circuit, the method comprising:
providing a first dielectric layer having formed therein a plurality of interconnects, wherein the plurality of interconnects includes at least a first interconnect and a second interconnect;
etching the first dielectric layer to form a plurality of recesses therein, wherein the plurality of recesses includes at least a first recess formed between the first and second interconnects; and
depositing a second dielectric layer over a topology formed by the plurality of recesses and the plurality of interconnects, wherein the second dielectric layer comprises a dielectric material of higher dielectric breakdown field (Ec) than the first dielectric layer.

### Claim 16 (depends on 15)

The method of claim 15 further comprising depositing a third dielectric layer over the second dielectric layer, wherein the first and third dielectric layers comprise a similar dielectric material.

### Claim 17 (depends on 15)

The method of claim 15 further comprising planarizing the first dielectric layer and the plurality of interconnects prior to etching the first dielectric layer to form the plurality of recesses therein.

### Claim 18 (depends on 17)

The method of claim 17, wherein planarizing the first dielectric layer and the plurality of interconnects comprises using a chemical-mechanical planarization (CMP) process.

### Claim 19 (depends on 15)

The method of claim 15, wherein etching the first dielectric layer to form the plurality of recesses therein comprises using an etch process utilizing fluorine (F)-based etch chemistry.

### Claim 20 (depends on 15)

An integrated circuit formed by the method of claim 15.

### Claim 21 (depends on 20)

An electronic device comprising the integrated circuit of claim 20.

### Claim 22

An integrated circuit comprising:
a first dielectric layer having formed therein a plurality of copper (Cu) interconnects and a plurality of recesses, wherein each recess of the plurality of recesses is formed between a different pair of adjacent interconnects of the plurality of interconnects; and
a second dielectric layer deposited over a topology formed by the plurality of recesses and the plurality of interconnects, wherein the second dielectric layer:
comprises a material of higher dielectric breakdown field (Ec) than the first dielectric layer;
reduces diffusion of the copper (Cu) into the first dielectric layer; and
reduces dielectric breakdown between adjacent interconnects.

### Claim 23

An integrated circuit interconnect comprising:
an insulator structure;
first and second metal features partially within the insulator structure, the first and second metal features each having a portion at least partially protruding beyond a surface of the insulator structure; and
a continuous, conformal insulation layer on the insulator structure and covering the portions of the first and second metal features at least partially protruding beyond the surface of the insulator structure, such that the conformal insulation layer fully encloses vertices of the protruding portions of the first and second metal features.