# US 2014/0151887 A1 · Memory Device Interconnects and Method of Manufacture

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- Number: US 2014/0151887 A1
- Document ID: US20140151887A1
- Status: Published application
- Kind: A1
- Application number: 14/102,446
- Filed: 2013-12-10
- Published: 2014-06-05
- Earliest claimed: 2008-05-06
- Assignees: Spansion LLC
- Applicants: Spansion LLC
- Inventors: Shenqing Fang; Connie WANG; Wen Yu; Fei Wang
- Web page: https://patentgrep.com/patent/US20140151887A1

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 41/10: characterised by the top-view layout
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/10: characterised by the top-view layout
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10W 20/084: {for dual-damascene structures}
- H10W 20/088: {involving partial etching of via holes}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An integrated circuit memory device, in one embodiment, includes a substrate having a plurality of bit lines. A first and second inter-level dielectric layer are successively disposed on the substrate. Each of a plurality of source lines and staggered bit line contacts extend through the first inter-level dielectric layer. Each of a plurality of source line vias and a plurality of staggered bit line vias extend through the second inter-level dielectric layer to each respective one of the plurality of source lines and the plurality of staggered bit line contacts. The source lines and staggered bit line contacts that extend through the first inter-level dielectric layer are formed together by a first set of fabrication processes. The source line vias and staggered bit line contacts that extend through the second inter-level dielectric layer are also formed together by a second set of fabrication processes.

## Claims

### Claim 1

An integrated circuit memory device comprising:
a substrate having a plurality of bit lines;
a first inter-level dielectric layer disposed on the substrate and on the plurality of bit lines;
a second inter-level dielectric layer disposed on the first inter-level dielectric layer;
a plurality of source lines that extend through the first inter-level dielectric layer;
a plurality of source line vias that extend through the second inter-level dielectric layer to each respective one of the plurality of source lines;
a plurality of bit line contacts that extend through the first inter-level dielectric layer to each respective one of the plurality of bit lines;
a plurality of bit line vias that extend through the second inter-level dielectric layer to each one of the plurality of bit line contacts; and
a metallization layer coupled to one or more of the plurality of source line vias and one or more of the plurality of bit line vias.

### Claim 2 (depends on 1)

The integrated circuit memory device of claim 1, wherein the plurality of bit line contacts and the plurality of source lines are formed from a first metal layer.

### Claim 3 (depends on 2)

The integrated circuit memory device of claim 2, wherein the plurality of bit line vias and the plurality of source line vias are formed from a second metal layer.

### Claim 4 (depends on 1)

The integrated circuit memory device of claim 1, wherein the plurality of bit line contacts and plurality of bit line vias are staggered so that adjacent ones of the bit line contacts and bit line vias are not in a same row.

### Claim 5 (depends on 1)

The integrated circuit memory device of claim 1, wherein the plurality of bit line contacts, the plurality of bit line vias, the plurality of source lines and the plurality of source line vias are formed from a metal or metal alloy.

### Claim 6 (depends on 1)

The integrated circuit memory device of claim 1, wherein the plurality of bit line contacts, the plurality of bit line vias, the plurality of source lines and the plurality of source line vias are comprised of one or more metals selected from the group consisting of tungsten, titanium, and titanium nitride.

### Claim 7 (depends on 1)

The integrated circuit memory device of claim 1, wherein each of the plurality of bit line contacts and each of the plurality of bit line vias are tapered.

### Claim 8 (depends on 1)

The integrated circuit memory device of claim 1, wherein each of the plurality of source lines and each of the plurality of source line vias are tapered.

### Claim 9

A method of fabricating an integrated circuit memory device comprising:
depositing a first inter-level dielectric layer on a substrate having a plurality of bit lines and on the plurality of bit lines;
etching a plurality of source line trenches in the first inter-level dielectric layer and a plurality of staggered bit line contact openings in the first inter-level dielectric layer that each extend to a respective one of the plurality of bit lines;
forming a plurality of source lines in the plurality of source line trenches and a plurality of staggered bit line contacts in the plurality of staggered bit line contact openings from a first metal layer;
depositing a second inter-level dielectric layer on the first inter-level dielectric layer;
etching a plurality of source line via openings in the second inter-level dielectric layer that each extend to a respective one of the plurality of source lines and a plurality of staggered bit line via openings in the second inter-level dielectric layer that each extend to a respective one of the plurality of staggered bit line contacts; and
forming a plurality of source line vias in the plurality of source line via openings and a plurality of staggered bit line vias in the plurality of staggered bit line via openings from a second metal layer.

### Claim 10 (depends on 9)

The method according to claim 9, wherein forming the plurality of source lines and the plurality of staggered bit line contacts comprises:
depositing the first metal layer after etching the source line trenches and the staggered bit line contact openings; and
removing a portion of the first metal layer until the first metal layer only remains in the source line trenches and the staggered bit line contact openings.

### Claim 11 (depends on 9)

The method according to claim 9, wherein forming the plurality of source line vias and the plurality of staggered bit line vias comprises:
depositing the second metal layer after etching the source line via openings and the staggered bit line via openings; and
removing a portion of the second metal layer until the second metal layer only remains in the source line via openings and staggered bit line via openings.

### Claim 12 (depends on 9)

The method according to claim 9, wherein:
the source line trenches and the staggered bit line contact openings are etched using a first mask; and
the source line via openings and the staggered bit line via openings are etched using a second mask.

### Claim 13 (depends on 9)

The method according to claim 9, further comprising:
depositing a first metallization oxide layer on the second inter-level dielectric layer;
etching a plurality of trenches in the first metallization oxide layer that extend to a respective one of the plurality of source line vias and the plurality of staggered bit line vias; and
forming a first metallization layer in the plurality of trenches.

### Claim 14 (depends on 9)

The method according to claim 9, wherein each of the plurality of bit line contacts and each of the plurality of bit line vias are tapered.

### Claim 15

A method of fabricating an integrated circuit memory device comprising:
depositing a first inter-level dielectric layer on a substrate having a plurality of bit lines and on the plurality of bit lines of the substrate;
etching a plurality of source line trenches in the first inter-level dielectric layer and a plurality of staggered bit line contact openings through the first inter-level dielectric layer to a respective one of the plurality of bit lines;
forming a plurality of source lines in the plurality of source line trenches and a plurality of staggered bit line contacts in the plurality of staggered bit line contact openings from a first metal layer;
depositing a second inter-level dielectric layer on the first inter-level dielectric layer;
depositing an etch stop layer on the first inter-level dielectric layer,
etching a plurality of source line via windows and a plurality of bit line via windows in the etch stop layer proximate the source lines and the staggered bit line contacts respectively;
depositing a first metallization oxide layer on the etch stop layer;
etching a plurality of trenches in the first metallization oxide layer that extend to a respective one of the plurality of source line vias windows and the plurality of staggered bit line vias windows in the etch stop layer, a plurality of the source line via openings through the second inter-level dielectric layer to a respective one of the plurality of the source lines, and a plurality of staggered bit line via openings through the second inter-level dielectric layer to a respective one of the plurality of staggered bit line contacts; and
forming a plurality of source line vias in the plurality of source line via openings, a plurality of staggered bit line vias in the plurality of staggered bit line via openings and a first metallization layer in the plurality of trenches in the first metallization oxide layer from a second metal layer.

### Claim 16 (depends on 15)

The method according to claim 15, wherein forming the plurality of source lines and the plurality of staggered bit line contacts comprises:
depositing the first metal layer after etching the source line trenches and the staggered bit line contact openings; and
removing a portion of the first metal layer until the first metal layer only remains in the source line trenches and the staggered bit line contact openings.

### Claim 17 (depends on 15)

The method according to claim 15, wherein forming the source line vias, the plurality of staggered bit line vias and the first metallization layer comprises depositing the second metal layer using an additive metal depositing technique.

### Claim 18 (depends on 15)

The method according to claim 15, wherein the first metal layer is tungsten, titanium, titanium nitrate or a multilayer of titanium, titanium nitride and tungsten.

### Claim 19 (depends on 15)

The method according to claim 15, wherein the second metal layer is tungsten, titanium, titanium nitrate or a multilayer of titanium, titanium nitride and tungsten.

### Claim 20 (depends on 15)

The method according to claim 15, wherein each of the plurality of staggered bit line contacts and each of the plurality of staggered bit line vias are tapered.