# US 2014/0151886 A1 · Semiconductor element and method for manufacturing semiconductor element

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- Number: US 2014/0151886 A1
- Document ID: US20140151886A1
- Status: Published application
- Kind: A1
- Application number: 14/233,388
- Filed: 2012-07-19
- Published: 2014-06-05
- Earliest claimed: 2011-07-19
- Assignees: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
- Inventors: Takeaki Maeda; Hiroyuki Okuno; Yoshihiro Yokota
- Web page: https://patentgrep.com/patent/US20140151886A1

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/01: Manufacture or treatment
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/032: {of conductive barrier, adhesion or liner layers}
- H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition}
- H10D 12/441: {Vertical IGBTs}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 64/0113: {the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers}
- H10P 14/44: Physical vapour deposition [PVD]
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a semiconductor element in which atomic interdiffusion between a semiconductor region and an electrode is suppressed and increase in the contact resistance is suppressed even in cases where the semiconductor element is exposed to high temperatures during the production processes or the like. A semiconductor element of the present invention is provided with: a semiconductor region that contains silicon; an electrode that contains aluminum; and a diffusion barrier layer that is interposed between the semiconductor region and the electrode and contains germanium. The germanium content in at least a part of the diffusion barrier layer is 4 at % or more.

## Claims

### Claim at position 1

1-6. (canceled)

### Claim 7

A semiconductor element comprising
a semiconductor region including silicon,
an electrode including aluminum, and
a diffusion barrier layer including germanium between the semiconductor region and the electrode;
wherein an amount of germanium contained in at least a part of the diffusion barrier layer is 4 atomic percent or more and 50 atomic percent or less,
a ratio of the amount of silicon to the amount of germanium in the diffusion barrier layer is 0.3 or more and 3.0 or less, and
a thickness of the diffusion barrier layer is 1 nm or more and 5 nm or less.

### Claim 8 (depends on 7)

A semiconductor according to claim 7 wherein;
an amount of germanium contained in at least a part of the diffusion barrier layer is 20 atomic percent or more and 30 atomic percent or less.

### Claim 9 (depends on 7, 8)

A manufacturing method of a semiconductor element according to claim 7 or claim 8 comprising;
a process step to form an aluminum alloy comprising germanium on a surface of semiconductor region containing silicon, and
a process step to conduct a heat treatment of the semiconductor region on which the aluminum alloy is formed.

### Claim 10 (depends on 9)

A semiconductor element fabricated by the method according to claim 9.