# US 2014/0151885 A1 · Semiconductor device and method for manufacturing a semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151885 A1 - Document ID: US20140151885A1 - Status: Published application - Kind: A1 - Application number: 14/012,211 - Filed: 2013-08-28 - Published: 2014-06-05 - Earliest claimed: 2012-08-28 - Assignees: Robert Bosch GmbH - Inventors: Peter SCHMOLLNGRUBER; Hubert BENZEL; Hans ARTMANN; Viktor MOROSOW - Web page: https://patentgrep.com/patent/US20140151885A1 ## CPC - H10W 20/425: {Barrier, adhesion or liner layers} - G01L 19/0069: {from the sensor to its support} - G01L 19/0627: {Protection against aggressive medium in general} - H10W 20/038: {covering conductive structures (H10W20/037 takes precedence)} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 74/134: {the encapsulations being in grooves in the semiconductor body} - H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/652: Cross-sectional shapes - H10W 70/654: Top-view layouts - H10W 70/655: Fan-out layouts - H10W 70/68: Shapes or dispositions thereof - H10W 72/536: {the connected ends being ball-shaped} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/9223: {with redistribution layers [RDL]} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9232: {with additional elements interposed between layers} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/983: {Reinforcing structures, e.g. collars} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G01L: MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE (weighing G01G) ## Abstract A semiconductor device includes a substrate which has at least one doped contact area and at least one line which is formed on the substrate and which is electrically connected to the at least one contact area, and at least one diffusion barrier, which includes at least one metal applied on a contact surface of the associated contact area, being formed between the at least one line and the at least one associated contact area, the at least one metal forming multiple metal-plated subareas which contact the contact surface of the same contact area and which are separated from one another. Furthermore, a manufacturing method for a semiconductor device is described. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate having at least one doped contact area; and at least one line formed on the substrate and electrically connected to the at least one contact area, at least one diffusion barrier, which includes at least one metal applied on a contact surface of the associated contact area, being formed between the at least one line and the at least one associated contact area; wherein the at least one metal forms multiple metal-plated subareas which contact the contact surface of the same contact area and which are separated from one another. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the multiple metal-plated subareas which contact the contact surface of the same contact area are offset laterally. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein at least one gap between two metal-plated subareas, which contact the contact surface of the same contact area and are adjacent to one another, is filled with at least one other material than the at least one metal of metal-plated subareas. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the material filled into the at least one gap includes at least one diffusion barrier material. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the at least one metal includes titanium, tantalum, platinum, chromium, and/or aluminum. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the at least one diffusion barrier includes a one-piece metal-plated contact layer which contacts multiple metal-contact subareas contacting the contact surface of the associated contact area. ### Claim 7 (depends on 6) The semiconductor device according to claim 6, wherein the one-piece metal-plated contact layer is a tantalum layer. ### Claim 8 (depends on 6) The semiconductor device according to claim 6, wherein the at least one metal is platinum. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the at least one diffusion barrier includes multiple metal-plated contact sublayers which are separated from one another, each metal-plated contact sublayer contacting one of multiple metal-plated subareas contacting the contact surface of the associated contact area. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the metal-plated contact sublayers are made of titanium nitride. ### Claim 11 (depends on 9) The semiconductor device according to claim 9, wherein the at least one metal is titanium. ### Claim 12 A manufacturing method for a semiconductor device, comprising: forming at least one diffusion barrier on at least one doped contact area of a substrate, at least one metal being applied on a contact surface of the associated contact area; forming at least one line on the substrate such that the at least one diffusion barrier lies between the at least one line and the at least one contact area, and the at least one line is electrically connected to the at least one contact area; and forming from the at least one metal multiple metal-plated subareas which contact the contact surface of the same contact area and which are separated from one another. ### Claim 13 (depends on 12) The method according to claim 12, further comprising: forming a one-piece metal-plated contact layer of the at least one diffusion barrier which contacts the multiple metal-plated subareas contacting the contact surface of the same contact area. ### Claim 14 (depends on 12) The method according to claim 12, further comprising: forming multiple metal-plated contact sublayers, which are separated from one another, of the at least one diffusion barrier, each metal-plated contact sublayer contacting one metal-plated subarea of the multiple metal-plated subareas contacting the contact surface of the same contact area.