# US 2014/0151884 A1 · Self-forming barrier structure and semiconductor device having the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151884 A1 - Document ID: US20140151884A1 - Status: Published application - Kind: A1 - Application number: 13/865,847 - Filed: 2013-04-18 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Industrial Technology Research Institute - Applicants: Industrial Technology Research Institute - Inventors: Wen-Hsi Lee; Chia-Yang Wu - Web page: https://patentgrep.com/patent/US20140151884A1 ## CPC - H10W 20/425: {Barrier, adhesion or liner layers} - H10P 14/44: Physical vapour deposition [PVD] - H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers} - H10W 20/0526: {by thermal treatment thereof} - H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition} - H10W 20/0552: {by diffusing metallic dopants to react with dielectrics} - H10W 20/076: {in via holes or trenches} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A self-forming barrier structure and a semiconductor device using the same are disclosed. The self-forming barrier structure includes a silicon-containing substrate; a first barrier layer formed on the silicon-containing substrate; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper. ## Claims ### Claim 1 A self-forming barrier structure comprising: a silicon-containing substrate; a first barrier layer formed on the silicon-containing substrate; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper. ### Claim 2 (depends on 1) The self-forming barrier structure according to claim 1, wherein the silicon-containing substrate comprises silicon, silicon oxide, or the combination thereof ### Claim 3 (depends on 1) The self-forming barrier structure according to claim 1, wherein the first barrier layer comprises ruthenium nitride (RuN). ### Claim 4 (depends on 3) The self-forming barrier structure according to claim 3, wherein the first barrier layer is formed on the silicon-containing substrate by sputtering ruthenium in a chamber filled with nitrogen gas. ### Claim 5 (depends on 3) The self-forming barrier structure according to claim 3, wherein the first barrier layer is configured for improving thermal stability of the barrier structure. ### Claim 6 (depends on 1) The self-forming barrier structure according to claim 1, wherein the second barrier layer comprises copper-manganese (CuMn) alloy. ### Claim 7 (depends on 6) The self-forming barrier structure according to claim 6, wherein the second barrier layer further functions as a copper crystal seed. ### Claim 8 (depends on 6) The self-forming barrier structure according to claim 6, wherein a part of manganese (Mn) atoms in the second barrier layer penetrate through the first barrier layer to the silicon-containing substrate, so as to fill up recesses on the silicon-containing substrate. ### Claim 9 (depends on 8) The self-forming barrier structure according to claim 8, further comprising a third barrier layer formed of manganese-silicon (MnSi) oxide due to a reaction between the silicon-containing substrate and the part of manganese (Mn) atoms penetrating through the first barrier layer. ### Claim 10 (depends on 3) The self-forming barrier structure according to claim 3, wherein the first barrier layer has a thickness in the range between 1 nm and 10 nm. ### Claim 11 (depends on 6) The self-forming barrier structure according to claim 6, wherein the second barrier layer has a thickness in the range between 50 nm and 150 nm. ### Claim 12 A semiconductor device having a self-forming barrier, comprising: a trenched semiconductor structure; a first barrier layer formed on the trenched semiconductor structure; and a second barrier layer formed of a copper-containing alloy on the first barrier layer; wherein the copper-containing alloy comprises copper and at least one other metal which diffuses faster than copper and is not inter-miscible with copper. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein the trenched semiconductor structure comprises at least one layer of dielectric. ### Claim 14 (depends on 12) The semiconductor device according to claim 12, wherein the first barrier layer comprises ruthenium nitride (RuN). ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein the first barrier layer is formed on the trenched semiconductor structure by sputtering ruthenium in a chamber filled with nitrogen gas. ### Claim 16 (depends on 14) The semiconductor device according to claim 14, wherein the first barrier layer is configured for improving thermal stability of the barrier structure. ### Claim 17 (depends on 12) The semiconductor device according to claim 12, wherein the second barrier layer comprises copper-manganese (CuMn) alloy. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the second barrier layer further functions as a copper crystal seed. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, wherein a part of manganese (Mn) atoms in the second barrier layer penetrate through the first barrier layer to the trenched semiconductor structure, so as to fill up recesses on the trenched semiconductor structure. ### Claim 20 (depends on 19) The semiconductor device according to claim 19, further comprising a third barrier layer formed of manganese-silicon (MnSi) oxide due to a reaction between the trenched semiconductor structure and the part of manganese (Mn) atoms penetrating through the first barrier layer. ### Claim 21 (depends on 14) The semiconductor device according to claim 14, wherein the first barrier layer has a thickness in the range between 1 nm and 10 nm. ### Claim 22 (depends on 17) The semiconductor device according to claim 17, wherein the second barrier layer has a thickness in the range between 50 nm and 150 nm.