# US 2014/0151882 A1 · Three-dimensional integrated circuit having stabilization structure for power supply voltage, and method for manufacturing same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151882 A1 - Document ID: US20140151882A1 - Status: Published application - Kind: A1 - Application number: 14/232,024 - Filed: 2013-04-10 - Published: 2014-06-05 - Earliest claimed: 2012-05-10 - Assignees: Panasonic Corporation - Applicants: Panasonic Corporation - Inventors: Takashi Morimoto - Web page: https://patentgrep.com/patent/US20140151882A1 ## CPC - H10W 70/65: Shapes or dispositions of interconnections - H10D 1/043: {using patterning processes to form electrode extensions, e.g. etching} - H10D 1/714: {having horizontal extensions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 88/00: Three-dimensional [3D] integrated devices - H10D 88/01: {Manufacture or treatment} - H10W 20/427: {Power or ground buses} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 90/00: Package configurations - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The three-dimensional integrated circuit has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further includes a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip. ## Claims ### Claim 1 A three-dimensional integrated circuit comprising: a first semiconductor chip; and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the first semiconductor chip and the second semiconductor chip is provided with a power supply wiring layer which has a wiring pattern structure for stably supplying a power supply voltage to an internal circuit of the semiconductor chip, and a ground wiring layer in succession, and one of the first semiconductor chip and the second semiconductor chip further comprises a second ground wiring layer or a second power supply wiring layer on a surface facing to the other semiconductor chip. ### Claim 2 (depends on 1) The three-dimensional integrated circuit according to claim 1, further comprising a decoupling capacitor formed between the second ground wiring layer or the second power supply wiring layer of the one of the first semiconductor chip and the second semiconductor chip and the power supply wiring layer or the ground wiring layer of the other semiconductor chip. ### Claim 3 (depends on 1) The three-dimensional integrated circuit according to claim 1, further comprising a decoupling capacitor formed between the power supply wiring layer and the ground wiring layer in each of the first semiconductor chip and the second semiconductor chip. ### Claim 4 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the power supply wiring layer and the ground wiring layer are provided on a surface facing the opposite semiconductor chip in each of the first semiconductor chip and the second semiconductor chip. ### Claim 5 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the one of the first semiconductor chip and the second semiconductor chip has the power supply wiring layer or the ground wiring layer immediately under the second ground wiring layer or the second power supply wiring layer, and the one of the first semiconductor chip and the second semiconductor chip further comprises a decoupling capacitor formed between the second ground wiring layer or the second power supply wiring layer and the power supply wiring layer or the ground wiring layer immediately under the second ground wiring layer or the second power supply wiring layer. ### Claim 6 (depends on 1) The three-dimensional integrated circuit according to claim 1, further comprising four pairs of the power supply wiring layer and the ground wiring layer which are opposite to each other or the ground wiring layer and the power supply wiring layer which are opposite to each other. ### Claim 7 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the wiring pattern structure of the power supply wiring layer includes mesh-like metal wiring. ### Claim 8 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the wiring pattern structure of the power supply wiring layer includes a power supply ring which encloses the wiring pattern structure and a strap which vertically or horizontally connects an inner surface of the power supply ring. ### Claim 9 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the first semiconductor chip and the second semiconductor chip have same transistor layers. ### Claim 10 (depends on 1) The three-dimensional integrated circuit according to claim 1, wherein the power supply wiring layer and the ground wiring layer correspond to global wiring layers. ### Claim 11 (depends on 1) The three-dimensional integrated circuit according to claim 1, further comprising a substrate supporting the whole of the three-dimensional integrated circuit. ### Claim 12 (depends on 1) The three-dimensional integrated circuit according to claim 1, further comprising a third semiconductor chip, wherein the third semiconductor chip is stacked to the first semiconductor chip or the second semiconductor chip. ### Claim 13 (depends on 12) The three-dimensional integrated circuit according to claim 12, wherein the third semiconductor chip is provided between the substrate and the first semiconductor chip or the second semiconductor chip, and the three-dimensional integrated circuit comprises the second ground wiring layer or the second power supply wiring layer between the first semiconductor chip and the second semiconductor chip which are far from the substrate. ### Claim 14 (depends on 12) The three-dimensional integrated circuit according to claim 12, wherein the first semiconductor chip or the second semiconductor chip is provided to be in contact with the substrate, the third semiconductor chip is provided on one of the first semiconductor chip and the second semiconductor chip which is not in contact with the substrate, and the first semiconductor chip or the second semiconductor chip which is provided to be in contact with the substrate consumes a higher current than the third semiconductor chip. ### Claim 15 (depends on 1) A processor device which includes the three-dimensional integrated circuit according to claim 1. ### Claim 16 A fabrication method of a three-dimensional integrated circuit which has a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip, comprising: forming a first semiconductor chip by stacking a transistor layer and a wiring layer which includes a ground wiring layer and a power supply wiring layer; forming a second semiconductor chip by further stacking a second ground wiring layer or a second power supply wiring layer by using a part of the first semiconductor chip which is obtained in the step of forming the first semiconductor chip; and forming a three-dimensional integrated circuit by bonding a surface of the wiring layer of the first semiconductor chip with the second ground wiring layer or the second power supply wiring layer of the second semiconductor chip to be opposite to each other.