# US 2014/0151881 A1 · Packaged semiconductor chips with array

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- Number: US 2014/0151881 A1
- Document ID: US20140151881A1
- Status: Published application
- Kind: A1
- Application number: 14/177,527
- Filed: 2014-02-11
- Published: 2014-06-05
- Earliest claimed: 2006-11-22
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Andrey Grinman; David Ovrutsky; Charles Rosenstein; Vage Oganesian
- Web page: https://patentgrep.com/patent/US20140151881A1

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 42/25: against alpha rays, e.g. for outer space applications
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/40: characterised by their materials
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/635: {Through-vias}
- H10W 70/688: {Flexible insulating substrates}
- H10W 72/01331: {using blanket deposition}
- H10W 72/801: {Interconnections on sidewalls of containers}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A chip-sized, wafer level packaged device including a portion of a semiconductor wafer including a device, at least one packaging layer containing silicon and formed over the device, a first ball grid array formed over a surface of the at least one packaging layer and being electrically connected to the device and a second ball grid array formed over a surface of the portion of the semiconductor wafer and being electrically connected to the device.

## Claims

### Claim 1

A chip-sized, wafer level packaged device comprising:
a portion of a semiconductor wafer including a device;
at least one packaging layer containing silicon and formed over said device;
a first ball grid array formed over a surface of said at least one packaging layer and being electrically connected to said device; and
a second ball grid array formed over a surface of said portion of said semiconductor wafer and being electrically connected to said device.