# US 2014/0151880 A1 · Package-on-package structures

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- Number: US 2014/0151880 A1
- Document ID: US20140151880A1
- Status: Published application
- Kind: A1
- Application number: 14/176,695
- Filed: 2014-02-10
- Published: 2014-06-05
- Earliest claimed: 2011-08-19
- Assignees: Marvell World Trade Ltd.
- Applicants: Marvell World Trade Ltd.
- Inventors: Huahung Kao; Shiann-Ming Liou
- Web page: https://patentgrep.com/patent/US20140151880A1

## CPC

- H10W 90/00: Package configurations
- H10W 40/778: {in encapsulations}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 40/251: {Organics}
- H10W 40/735: {by melting or evaporation of solids}
- H10W 44/248: {for antennas}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/354: {comprising polymers}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure provide a package on package arrangement comprising a first package including a substrate layer including a top side, and a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and a first die coupled to the bottom side of the substrate layer. The arrangement also comprises a second package including a plurality of rows of solder balls and at least one of one or both of an active component or a passive component. The second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package. The active component and/or a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package.

## Claims

### Claim 1

A package on package arrangement comprising:
a first package including
a substrate layer including (i) a top side, and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and
a first die coupled to the bottom side of the substrate layer;
a second package including a plurality of rows of solder balls; and
at least one of one or both of (i) an active component or (ii) a passive component,
wherein the second package is attached, via the plurality of rows of solder balls, to the substantially flat surface of the top side of the substrate layer of the first package, and
wherein the at least one of one or both of (i) an active component or (ii) a passive component is attached to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 2 (depends on 1)

The package on package arrangement of claim 1, further comprising:
a second die attached to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 3 (depends on 2)

The package on package arrangement of claim 2, wherein:
the second die is wire bonded to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 4 (depends on 2)

The package on package arrangement of claim 2, wherein:
the second die is attached to the substantially flat surface of the top side of the substrate layer of the first package via a flip-chip process.

### Claim 5 (depends on 1)

The package on package arrangement of claim 1, further comprising:
an adhesive layer located between the first die and the substrate layer,
wherein the adhesive layer attaches the first die to the bottom side of the substrate layer of the second package.

### Claim 6 (depends on 1)

The package on package arrangement of claim 1, further comprising:
a bond pad located on the bottom side of the first die; and
a substrate pad located on the bottom side of the substrate layer of the second package,
wherein the bond pad of the die is coupled, via a wire, to the substrate pad of the substrate layer to route electrical signals of the first die.

### Claim 7 (depends on 1)

The package on package arrangement of claim 1, wherein the plurality of rows of solder balls comprises first solder balls and the package on package arrangement further comprises:
second solder balls attached to the bottom side of the substrate layer to electrically connect the first die to the substrate layer of the second package; and
an underfill material located between the second solder balls and the substrate layer of the second package.

### Claim 8 (depends on 1)

The package on package arrangement of claim 1, wherein the plurality of rows of solder balls comprises first solder balls and the package on package arrangement further comprises:
second solder balls attached to a bottom side of the second package; and
the second solder balls are located around a periphery of the second package to thereby form a ball grid array.

### Claim 9 (depends on 1)

The package on package arrangement of claim 1, wherein:
the plurality of rows of solder balls comprises first solder balls;
the substrate layer comprises a first substrate layer;
the first package further comprises a second die arranged next to the first die; and
each of the first die and the second die is connected to a second substrate layer in the first package via second solder balls.

### Claim 10 (depends on 1)

The package on package arrangement of claim 1, further comprising:
thermal interface material attached to a bottom side of the first die.

### Claim 11 (depends on 10)

The package on package arrangement of claim 10, further comprising:
thermal conductive material attached to the thermal interface material.

### Claim 12 (depends on 11)

The package on package arrangement of claim 11, wherein the thermal interface material comprises one of a film, a grease composition, or an underfill material.

### Claim 13 (depends on 1)

The package on package arrangement of claim 1, further comprising:
one of (i) an interposer or (ii) a printed circuit board attached to a bottom side of the die.

### Claim 14 (depends on 1)

The package on package arrangement of claim 1, wherein:
the plurality of rows of solder balls comprises a first plurality of rows of solder balls;
the package on package arrangement further comprises a third package including a second plurality of rows of solder balls;
the first package is attached, via the first plurality of rows of solder balls, to the substantially flat surface of the second package; and
the third package is attached, via the second plurality of rows of solder balls, to the substantially flat surface of the second package.

### Claim 15 (depends on 1)

The package on package arrangement of claim 1, wherein the plurality of rows of solder balls comprises first solder balls and the package on package arrangement further comprises:
second solder balls attached to the bottom side of the substrate layer and a top side of the first die; and
a plurality of through-silicon vias located in the first die, wherein the plurality of through-silicon vias respectively extend between
at least some of the second solder balls, and
a plurality of third solder balls that are attached to a bottom side of the bottom package.

### Claim 16

A method comprising:
providing a first package including a substrate layer, wherein the substrate layer includes (i) a top side and (ii) a bottom side that is opposite to the top side, wherein the top side of the substrate layer defines a substantially flat surface, and wherein the first package further includes a first die coupled to the bottom side of the substrate layer;
providing a second package having a plurality of rows of solder balls attached to a bottom surface of the second package;
attaching, via the plurality of rows of solder balls of the second package, the second package to the substantially flat surface of the first package; and
attaching at least one of one or both of (i) an active component or (ii) a passive component to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
attaching a second die to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 18 (depends on 17)

The method of claim 17, wherein the second die is wire bonded to the substantially flat surface of the top side of the substrate layer of the first package.

### Claim 19 (depends on 17)

The method of claim 17, wherein the second die is attached to the substantially flat surface of the top side of the substrate layer of the first package via a flip-chip process.

### Claim 20 (depends on 16)

The method of claim 16, wherein the attaching the first die to the bottom side of the substrate layer comprises attaching the first die to the bottom side of the substrate layer via an adhesive layer.

### Claim 21 (depends on 16)

The method of claim 16, wherein the plurality of rows of solder balls comprises first solder balls and the attaching the first die to the bottom side of the substrate layer comprises attaching the first die to the bottom side of the substrate layer via second solder balls.

### Claim 22 (depends on 21)

The method of claim 21, further comprising:
providing underfill material between space located (i) among the second solder balls and (ii) between the first die and the bottom side of the substrate layer of the first package.

### Claim 23 (depends on 16)

The method of claim 16, further comprising:
providing a bond pad on the first die, wherein the bond pad is positioned on a bottom side of the first die;
providing a substrate pad on the substrate layer, wherein the substrate pad is positioned on the bottom side of the substrate layer of the first package; and
coupling, via a wire bonding process, the bond pad on the first die to the substrate pad on the substrate layer to thereby route electrical signals of the first die.

### Claim 24 (depends on 16)

The method of claim 16, wherein the plurality of rows of solder balls comprises first solder balls and the method further comprises:
attaching second solder balls to a bottom side of the first package,
wherein the second solder balls are positioned on a right side and a left side of the first package.

### Claim 25 (depends on 16)

The method of claim 16, further comprising:
attaching a thermal interface material to a bottom side of the first die.

### Claim 26 (depends on 16)

The method of claim 16, wherein the plurality of rows of solder balls comprises first solder balls and the method further comprises:
attaching second solder balls on the bottom side of the substrate layer;
attaching the first die to the bottom side of the substrate layer via the second solder balls; and
providing through-silicon vias in the first die to connect the second solder balls to third solder balls attached to a bottom side of the first package.

### Claim 27 (depends on 16)

The method of claim 16, wherein the plurality of rows of solder balls comprises first solder balls and the method further comprises:
attaching second solder balls to a bottom side of the first die; and
coupling one of (i) an interposer or (ii) a printed circuit board to the second solder balls.

### Claim 28 (depends on 16)

The method of claim 16, wherein:
the plurality of rows of solder balls comprises a first plurality of rows of solder balls; and
the method further comprises
providing a third package having a second plurality of rows of solder balls attached to a bottom surface of the third package, and
attaching, via the second plurality of rows of solder balls, the third package to the substantially flat surface of the first package.