# US 2014/0151879 A1 · Stress-resilient chip structure and dicing process

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- Number: US 2014/0151879 A1
- Document ID: US20140151879A1
- Status: Published application
- Kind: A1
- Application number: 13/689,805
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Disco Corporation; International Business Machines Corporation
- Applicants: International Business Machines Corporation; Disco Corporation
- Inventors: Richard F. Indyk; Ian D. Melville; Shigefumi Okada
- Web page: https://patentgrep.com/patent/US20140151879A1

## CPC

- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10D 62/117: {Shapes of semiconductor bodies}
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/20: Conductive package substrates serving as an interconnection, e.g. metal plates (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/927: {Multiple bond pads having different structures}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 74/014: {using batch processing}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/721: {having structure or size changed during the connecting}
- H10W 80/732: {having shape changed during the connecting}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate includes a plurality of semiconductor chips arranged in a grid pattern and laterally spaced from one another by channel regions. The substrate includes a vertical stack of a semiconductor layer and at least one dielectric material layer embedding metal interconnect structures. The at least one dielectric material layer are removed along the channel regions and around vertices of the grid pattern so that each semiconductor chip includes corner surfaces that are not parallel to lines of the grid pattern. The corner surfaces can include straight surfaces or convex surfaces. The semiconductor chips are diced and subsequently bonded to a packaging substrate employing an underfill material. The corner surfaces reduce mechanical stress applied to the metal interconnect layer during the bonding process and subsequent thermal cycling processes.

## Claims

### Claim 1

A method of manufacturing a semiconductor structure, said method comprising:
forming at least one dielectric material layer embedding metal semiconductor structures on a semiconductor substrate, whereby a plurality of semiconductor chip cores and inter-chip regions are formed, wherein each of said plurality of semiconductor chip cores comprises a portion of said semiconductor substrate and a portion of said at least one dielectric material layer, and each of said plurality of semiconductor chip cores is arranged in a grid pattern;
removing portions of said at least one dielectric material layer from said inter-chip regions to form grooves in said at least one dielectric layer and to form corner surfaces of said plurality of semiconductor chip cores around vertices of said grid pattern, wherein each corner surface is not parallel to any of said two sets of parallel lines; and
dicing said semiconductor substrate along said grooves to form a plurality of semiconductor chips.

### Claim 2 (depends on 1)

The method of claim 1, wherein said corner surfaces are planar vertical surfaces that are not parallel to lines connecting said vertices of said grid pattern.

### Claim 3 (depends on 2)

The method of claim 2, wherein remaining portions of said at least one dielectric material layer within one of said plurality of semiconductor chip have an octagonal horizontal cross-sectional shape after said forming of said corner surfaces.

### Claim 4 (depends on 1)

The method of claim 1, wherein said corner surfaces are convex vertical surfaces.

### Claim 5 (depends on 4)

The method of claim 4, wherein remaining portions of said at least one dielectric material layer within one of said plurality of semiconductor chip have a cross-sectional shape of a rounded rectangle after said forming of said corner surfaces.

### Claim 6 (depends on 1)

The method of claim 1, wherein said grid pattern is defined by intersecting points of two sets of parallel lines, and said vertices are said intersecting points.

### Claim 7 (depends on 6)

The method of claim 6, wherein said inter-chip regions are located on said two sets of parallel lines.

### Claim 8 (depends on 1)

The method of claim 1, wherein each of said plurality of semiconductor chip cores is laterally spaced from one another by said inter-chip regions prior to said dicing.

### Claim 9 (depends on 1)

The method of claim 1, wherein said removing of said portions of said at least one dielectric material layer comprises ablating said portions of said at least one dielectric material layer by laser ablation.

### Claim 10 (depends on 1)

The method of claim 1, wherein each of said plurality of semiconductor chips includes a portion of said at least one dielectric material layer, said portion having vertical surfaces and a subset of said corner surfaces.

### Claim 11 (depends on 10)

The method of claim 10, wherein each of said plurality of semiconductor chips further comprises a portion of said semiconductor substrate that has vertical semiconductor surfaces located within vertical planes of said vertical surface of said portion of said at least one dielectric material layer, wherein said vertical semiconductor surfaces adjoin one another at vertical edges.

### Claim 12 (depends on 1)

The method of claim 1, further comprising bonding a semiconductor chip among said plurality of semiconductor chips with a bonding substrate with an underfill material between said semiconductor chip and said bonding substrate, wherein said underfill material contacts corner surfaces on said semiconductor chip.

### Claim 13 (depends on 12)

The method of claim 12, wherein said semiconductor chip comprises pairs of parallel sidewalls that laterally adjoin said corner surfaces and contact said underfill material.

### Claim 14

A semiconductor structure comprising a semiconductor chip, said semiconductor chip including a semiconductor substrate and at least one dielectric material layer that embeds metal interconnect structures, wherein said at least one dielectric material layer includes:
pairs of parallel vertical surfaces, and corner surfaces that are not parallel to said pairs of parallel vertical surfaces and adjoin said pairs of parallel vertical surfaces.

### Claim 15 (depends on 14)

The semiconductor structure of claim 14, wherein said semiconductor substrate has pairs of vertical semiconductor surfaces located within vertical planes of said pairs of parallel vertical surfaces of said at least one dielectric material layer, wherein said vertical semiconductor surfaces adjoin one another at vertical edges.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, further comprising a bonding substrate bonded to said semiconductor chip with an underfill material therebetween.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein said underfill material is in contact with said pairs of parallel vertical surfaces and said corner surfaces.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein said bonding substrate is bonded to said semiconductor chip through an array of solder balls.

### Claim 19 (depends on 14)

The semiconductor structure of claim 14, wherein said corner surfaces are planar vertical surfaces.

### Claim 20 (depends on 14)

The semiconductor structure of claim 14, wherein said corner surfaces are convex vertical surfaces.