# US 2014/0151878 A1 · System and Method for Fine Pitch PoP Structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0151878 A1 - Document ID: US20140151878A1 - Status: Published application - Kind: A1 - Application number: 14/175,668 - Filed: 2014-02-07 - Published: 2014-06-05 - Earliest claimed: 2012-02-17 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Cheng-Chung Lin; Hsiu-Jen Lin; Cheng-Ting Chen; Chun-Cheng Lin; Ming-Da Cheng; Chung-Shi Liu - Web page: https://patentgrep.com/patent/US20140151878A1 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection. ## Claims ### Claim 1 A semiconductor device comprising: a first substrate, the first substrate having a first semiconductor die coupled thereto; a second substrate, the second substrate having a second semiconductor die coupled thereto; and a plurality of electrical connections electrically coupling the first substrate to the second substrate, each of the electrical connections having a height-to-width ratio of between about 1 to about 4. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein each of the electrical connections have a width smaller in a middle region than regions adjacent the first substrate and the second substrate. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein each of the electrical connections has an interior core different from an exterior portion. ### Claim 4 (depends on 3) The semiconductor device of claim 3, wherein the exterior portion has a lower melting temperature than the interior core. ### Claim 5 (depends on 3) The semiconductor device of claim 3, wherein the interior core comprises a Cu core. ### Claim 6 (depends on 3) The semiconductor device of claim 3, wherein the interior core comprises a plastic core. ### Claim 7 (depends on 1) The semiconductor device of claim 1, further comprising a molding underfill positioned between the first substrate and the second substrate. ### Claim 8 A semiconductor device comprising: a first substrate, the first substrate having a first semiconductor die coupled thereto; a second substrate, the second substrate having a second semiconductor die coupled thereto; and a plurality of electrical connections electrically coupling the first substrate to the second substrate, each of electrical connections having an hourglass shape. ### Claim 9 (depends on 8) The semiconductor device of claim 8, further comprising a molding underfill interposed between the first substrate and the second substrate. ### Claim 10 (depends on 8) The semiconductor device of claim 8, wherein each of the electrical connections having a height-to-width ratio of between about 1 to about 4. ### Claim 11 (depends on 8) The semiconductor device of claim 8, wherein each of the electrical connections has an interior core different from an exterior portion. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the exterior portion has a lower melting temperature than the interior core. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein the interior core comprises a Cu core. ### Claim 14 (depends on 11) The semiconductor device of claim 11, wherein the interior core comprises a plastic core. ### Claim 15 A semiconductor device comprising: a first substrate, the first substrate having a first semiconductor die coupled thereto; a second substrate, the second substrate having a second semiconductor die coupled thereto; and a plurality of electrical connections electrically coupling the first substrate to the second substrate, each of the electrical connections having a first region and a second region along the first substrate and the second substrate, respectively, the first region and the second region being wider than an intermediate region interposed between the first region and the second region. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein each of the electrical connections has an interior core different from an exterior portion. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the interior core comprises a Cu core. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the interior core comprises a plastic core. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein the interior core has a different melting temperature than the exterior portion. ### Claim 20 (depends on 15) The semiconductor device of claim 15, further comprising a molding compound interposed between the first substrate and the second substrate.