# US 2014/0151877 A1 · Semiconductor package and method for fabricating the same

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- Number: US 2014/0151877 A1
- Document ID: US20140151877A1
- Status: Published application
- Kind: A1
- Application number: 14/175,162
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2009-10-26
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: HWAN-SIK LIM; Sunwon Kang; Jongho Lee
- Web page: https://patentgrep.com/patent/US20140151877A1

## CPC

- H10W 90/00: Package configurations
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/01: {Manufacture or treatment}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/227: {Multiple bumps having different sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/263: {Providing mechanical bonding or support, e.g. dummy bumps}
- H10W 72/267: {Multiple bump connectors having different functions}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/20: Configurations of stacked chips
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a semiconductor chip having a first bump group and a second bump group, and a package substrate having a first pattern for data communication with the semiconductor chip and a second pattern for supplying power to the semiconductor chip or grounding the semiconductor chip, wherein the first bump group is disposed on the first pattern and the second bump group is disposed on the second pattern.

## Claims

### Claim at position 1

-10. (canceled)

### Claim 11

A semiconductor package, comprising:
a substrate having a plurality of first patterns disposed in a first direction, each of the plurality of first patterns including a first land and a first extension extending along a second direction that is substantially perpendicular to the first direction, wherein a first real bump is disposed on the first land and a plurality of first dummy bumps are disposed on the first extension; and
a plurality of second patterns disposed in the first direction, each of the plurality of second patterns including a second land and a second extension, wherein a second real bump is disposed on the second land and a plurality of second dummy bumps are disposed on the second extension in the second direction,
wherein the plurality of first patterns is a mirror image of the plurality of second patterns with respect to an imaginary center line extending in the first direction through the center of the substrate.

### Claim 12 (depends on 11)

The package of claim 11, wherein the first and second real and dummy bumps are configured to support a semiconductor chip, and the first and second real bumps are electrically conductive.

### Claim 13 (depends on 11)

The package of claim 11, wherein there are at least three dummy bumps disposed on each first pattern or each second pattern.

### Claim 14 (depends on 11)

The package of claim 11, wherein there are at least six first patterns and at least six second patterns.

### Claim 15

A semiconductor package, comprising:
a package substrate having a plurality of patterns, each comprising a land and an extension extending from the land in a first direction, wherein the land is configured to receive a conductive bump and the extension is configured to receive a plurality of dummy bumps spaced at an equal distance from each other, and wherein the plurality of patterns are positioned with a first set of patterns in a second direction perpendicular to the first direction, and a second set of patterns in the second direction, the first set of patterns and the second set of patterns opposing each other with respect to an imaginary line extending in the second direction along the center of the package substrate.

### Claim 16 (depends on 15)

The semiconductor package of claim 15, wherein a width of the land is different from a width of the extension.

### Claim 17 (depends on 15)

The semiconductor package of claim 15, wherein the conductive bump is connected to an on-chip circuit via a pad, and the dummy bumps are disposed on an insulation layer.

### Claim 18 (depends on 15)

The semiconductor package of claim 15, wherein there are at least three dummy bumps disposed on each pattern.

### Claim 19 (depends on 15)

The semiconductor package of claim 15, wherein there are at least three patterns in the first set or the second set of patterns.

### Claim 20 (depends on 15)

The semiconductor package of claim 15, wherein there are at least six patterns in the first set or the second set of patterns.

### Claim 21

A semiconductor package, comprising:
a package substrate;
a semiconductor chip disposed on the package substrate, the semiconductor chip having a first bump group including a first real bump and a plurality of first dummy bumps and a second bump group including a second real bump and a plurality of second dummy bumps;
a first pattern disposed on the package substrate and connected to the first bump group, the first pattern including a first land and a first extension, wherein the first real bump is disposed on the first land, and the plurality of first dummy bumps is disposed on the first extension; and
a second pattern disposed on the substrate and connected to the second bump group, the second pattern including a second land and a second extension, wherein the second real bump is disposed on the second land, and the plurality of second dummy bumps is disposed on the second extension, and wherein the first pattern and the second pattern are spaced apart from each other and are disposed along a first line, and wherein the first pattern and the second pattern are substantially symmetrical with each other with respect to a center line between the first pattern and the second pattern, the center line substantially perpendicular with the first line.

### Claim 22 (depends on 21)

The semiconductor package of claim 21, wherein the plurality of first dummy bumps and the plurality of second dummy bumps are positioned between the first real bump and the second real bump.

### Claim 23 (depends on 21)

The semiconductor package of claim 21, wherein a data signal is transmitted through the first pattern to the semiconductor chip, and power is supplied to the semiconductor chip through the second pattern.

### Claim 24 (depends on 21)

The semiconductor package of claim 21, wherein the first extension extends from the first land along the first line, and the second extension extends from the second land along the first line.

### Claim 25 (depends on 21)

The semiconductor package of claim 21, wherein a width of the first land is larger than a width of the first extension.

### Claim 26 (depends on 21)

The semiconductor package of claim 21, wherein a width of the second land is larger than a width of the second extension.

### Claim 27 (depends on 21)

The semiconductor package of claim 21, wherein the first real bump provides an electrical signal path between the semiconductor chip and the first pattern, and the second real bump provides an electrical signal path between the semiconductor chip and the second pattern.

### Claim 28 (depends on 21)

The semiconductor package of claim 21, wherein the plurality of first dummy bumps and the plurality of second dummy bumps support the semiconductor chip on the substrate.